Senior Engineer, Analog IC Design

Marvell Technology•Santa Clara, CA

1d•$110,000 - $140,000

About The Position

As an Analog IC Design Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering provides IP to be used by all other business units, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

Requirements

Bachelor’s or foreign equivalent degree in Electrical Engineering, Materials Science, Physics/ Applied Physics, Computer Engineering, or a related field.
At least three (3) months of work/internship/project experience or completed coursework in deep sub-micron CMOS technologies.
At least three (3) months of work/internship/project experience or completed coursework in Analog-Digital Interfaces.
At least three (3) months of work/internship/project experience or completed coursework in implementing StrongARM latch comparator for better accuracy and low power consumption and capacitive DAC.
At least three (3) months of work/internship/project experience or completed coursework in using industry CAD tools including Cadence Spectre, SPICE, Verilog, HSPICE, and MATLAB for circuit modeling, analysis, and verification.
At least three (3) months of work/internship/project experience or completed coursework in applying low-power and high-speed design techniques to meet functional, power, and performance requirements.
At least three (3) months of work/internship/project experience or completed coursework in FPGA programming and data transfer between FPGA and PC.
At least three (3) months of work/internship/project experience or completed coursework in supporting the design and debugging of laboratory PCB test boards, including power regulation circuits, bias networks, clock distribution components, and high-speed signal routing.
At least three (3) months of work/internship/project experience or completed coursework in designing and analyzing high-speed receiver or transmitter building blocks such as CTLE, VGA, buffer stages, or clock/data recovery circuits.
At least three (3) months of work/internship/project experience or completed coursework in performing pre-layout and post-layout simulations, including parasitic extraction and corner (PVT) analysis.
At least three (3) months of work/internship/project experience or completed coursework in analyzing signal integrity metrics such as jitter, bandwidth, return loss, and eye diagram performance.
At least three (3) months of work/internship/project experience or completed coursework in designing biasing circuits and current mirrors, including mismatch analysis and device sizing considerations.
At least three (3) months of work/internship/project experience or completed coursework in working with high-frequency modeling and layout considerations, including parasitic capacitance, inductance, and EM effects.

Responsibilities

Design and optimize circuits to meet key performance targets.
Build transistor-level circuits from scratch or improve/port existing blocks using tools like Cadence.
Run simulations to evaluate various performance metrics and conduct circuit analysis to validate designs.
Handoff validated designs for physical layout, then verify post-layout performance through additional simulation and testing.
Perform laboratory testing and characterization of prototype silicon to verify functionality and compliance with design specifications.
Prepare documentation and support cross-functional development activities as needed.
Join weekly team meetings to discuss project progress, share updates, and collaboratively resolve design issues.
Present and review work with senior designers and managers, following designs through from concept to production.