Senior Emulation Engineer

Marvell Technology•Santa Clara, CA

5d•$158,600 - $237,600

About The Position

As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.

Requirements

BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).
Extensive knowledge of emulation platform offerings from leading vendors such as Synopsys, Cadence, and Siemens, with deep experience in building complex SoC emulation models.
Hands-on experience developing emulation models using platforms from Synopsys, Cadence, and Siemens is required.
Proficient in bringing up emulation models, including reset sequence execution and firmware bring-up.
Strong working knowledge in one or more of the following areas: processor architecture, SoC components, interconnect buses, I/O protocols (PCIe, CXL, Ethernet), and memory interface technologies (DDR, HBM).
Skilled in scripting languages such as Perl, Python, Tcl, and UNIX Shell.
Proven ability to define emulation strategy and platform requirements, develop emulation test plans, and drive verification execution for large-scale products on platforms such as Veloce, ZeBu, and Palladium.
Experience with System Verilog, UVM.
Experience with writing a detailed test plan
Good understanding of Linux O.S.

Nice To Haves

Understanding of networking protocols, a plus.
Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
Requires the ability to accept and work with differing opinions.
Cannot be a close-minded developer.
Must be able to learn on the fly and work in a fast-paced environment.

Responsibilities

Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
Developing tests and tuning the environment to achieve coverage goals.
Debugging failures and working with designers to resolve issues.
Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
Unit and regression testing of software tools.