Senior Electrical Engineer - Aggregator

Apptronik•Austin, TX

16h

About The Position

Apptronik is a human-centered robotics company developing AI-powered robots to support humanity in every facet of life. Our flagship humanoid robot, Apollo, is built to collaborate thoughtfully with people, starting with critical industries such as manufacturing and logistics, with future applications in healthcare, the home, and beyond. We operate at the cutting edge of Applied AI, applying our expertise across the full robotics stack to solve some of society's most important problems. You will join a team dedicated to bringing Apollo to market at scale, tackling the complex challenges like safety, commercialization, and mass production to change the world for the better. We're looking for a Senior Electrical Engineer to help design and build the electronics for Apollo's sensor bridge. Strong candidates will have experience with FPGA hardware for both PCBA design and RTL development. This role works closely with the perception team to give Apollo sight and enable critical safety functions. You'll take direct, hands-on ownership of defined subsystems within the board — schematic capture, layout guidance, and RTL blocks — executing against an architecture defined in partnership with the team's Staff and/or Principal engineers.

Requirements

Experience in FPGA hardware design for time-sensitive, high-performance applications (image processing, high-speed data acquisition, real-time networking, or similar), including: FPGA device selection and architecture definition
RTL development in VHDL and/or Verilog
High-speed interface design (CSI-2, GMSL/SerDes, Ethernet, PCIe, or comparable)
Timing closure, clock-domain crossing, and resource optimization
Integration of high-speed transceivers and external PHY devices
FPGA tool flows (Vivado, Quartus, or Lattice Radiant) and simulation (ModelSim/Questa or equivalent)
Understanding of high-speed digital design fundamentals: signal integrity, impedance-controlled routing, differential pairs, stack-up, and timing analysis across the board-to-FPGA boundary.
Experience with camera/image sensor hardware: SerDes (GMSL, FPD-Link, or similar), MIPI CSI-2, and ISP integration — automotive or robotics vision systems strongly preferred.
Experience with Ethernet-based sensor streaming and sensor bridges.
Excellent communication (verbal & written); will be expected to develop detailed build assembly instructions and diagrams.
Excellent problem-solving and hardware debugging skills.
Hands-on experience with prototyping and testing, including the use of lab equipment.
Ability to thrive in a fast-paced, high-growth environment where "perfect" is the enemy of "shipped," knowing exactly when a design is robust enough for the real world.
Bachelors, Masters, or PhD degree in Electrical Engineering or related field.
At least 5 years of experience in Electrical Engineering.

Responsibilities

Contribute to requirements definition and own part selection, schematic capture, layout guidance, and RTL implementation for assigned subsystems of a multi-Gbps, mixed-signal PCBA that aggregates camera sensor data and human-robot interface functions into an efficient cable interface routed across dynamic joints.
Carry the design through prototype, validation, and manufacturing release, in coordination with the engineer(s) owning overall board architecture.
Generate and maintain design documentation including: schematics, RTL documentation, test plans, and fab/assembly drawings.
Design and validate high-speed digital interfaces (CSI-2, GMSL2/FPD-Link/PoC, 10GbE) including signal integrity, impedance control, and length-matching.
Contribute to the board's power tree design for proper power sequencing and low-power consumption.
Design for EMC, ESD, and thermal constraints.
Develop RTL (VHDL/Verilog) for CSI-2 ingest, Ethernet packetization, timestamp/metadata insertion, and camera synchronization logic for deterministic multi-camera and multi-IMU synchronization, working within an FPGA architecture defined collaboratively with senior technical staff.
Support timing closure, clock-domain crossing, and resource/power budgeting for your RTL blocks.
Assist with integration of high-speed transceivers and external PHYs.
Develop and execute validation plans for your assigned subsystems, spanning board-level and FPGA-level testing.
Build test fixtures and use lab equipment (high-bandwidth oscilloscopes, protocol analyzers, logic analyzers) to validate latency, bandwidth, and synchronization requirements.
Debug across the hardware/RTL boundary — link training failures, timing violations, ISP misconfiguration, power sequencing faults — using rigorous, first-principles root-cause analysis, escalating and collaborating with technical leads on cross-subsystem issues.
Support the entire component lifecycle through PLM systems, managing third-party relationships with hardware vendors and contract manufacturers (CMs) to ensure successful production scaling and design-for-manufacturability (DFM/DFA).
Collaborate closely with cross-functional teams, including technical lead, project managers, software, mechanical, thermal, systems engineers, and manufacturing.
Act as a mentor within the electrical engineering team, guiding junior engineers on best practices for hardware design, documentation, and troubleshooting.
Execute assigned work streams reliably and communicate progress clearly to technical leads and program management.
Contribute to design reviews and root-cause analysis for hardware and software defect resolution within your scope.
Provide work breakdowns and time estimates for your own work to inform project execution, and raise design or schedule risks proactively.