Mixed-Signal)

Zealogics.com•San Jose, CA

34d

About The Position

We are seeking a highly skilled Senior Electrical Engineer with expertise in FPGA, High-Speed, and Mixed-Signal design. This role involves defining FPGA-centric system architectures, designing and integrating high-speed interfaces, mixed-signal and analog front-end circuits, and power systems. The engineer will also be responsible for schematic design, PCB implementation guidance, system bring-up, debug, and leading technical reviews. This position requires strong collaboration with cross-functional teams and mentoring junior engineers.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or related field.
8–12+ years of experience in high-speed, FPGA, or mixed-signal systems.
FPGA-based system design experience.
DDR4 memory subsystem design experience.
PCIe / SerDes / high-speed link experience.
ADC and analog front-end design experience.
DC/DC power system design experience.
Strong understanding of Signal Integrity (SI).
Strong understanding of Power Integrity (PI).
Strong understanding of High-speed timing and jitter analysis.

Nice To Haves

Hands-on experience with FPGA platforms (Intel / Xilinx).
Experience with high-speed data converters.
Experience with optical interfaces / QSFP modules.
Experience with JESD204 or similar high-speed data links.
Strong PCB design experience with high-speed constraints.
Experience with Xpedition (Mentor / Siemens).
Experience with SI/PI analysis tools.
Experience in semiconductor equipment, imaging, or instrumentation systems.
Experience with multi-board or modular systems.
Understanding of signal-power-thermal coupling effects.
Full product lifecycle experience (R&D → NPI → production).
Strong ownership mindset and accountability.
Ability to solve complex multi-domain engineering problems.
Excellent communication and cross-functional collaboration skills.

Responsibilities

Define FPGA-centric system architectures for high-throughput data processing platforms.
Partition functionality across FPGA, ADC/DAC, and host interfaces.
Collaborate with FPGA/FW teams on interface definition, timing, and performance.
Design and integrate high-speed interfaces including DDR4/DDR memory subsystems, PCIe Gen3/Gen4 interfaces, QSFP (10G/25G/40G/100G) links, and 10G+ SerDes channels.
Define routing constraints, stack-up, and impedance control.
Ensure signal integrity, timing closure, and link stability.
Design and integrate high-speed ADC/DAC signal chains, Data Converter Architectures (DCA), and precision analog front-end (AFE) circuits.
Develop circuits using low-noise OpAmps, filters, and gain stages.
Optimize performance metrics such as SNR, ENOB, bandwidth, and jitter sensitivity.
Design multi-rail DC/DC power systems for FPGA and high-speed circuits.
Manage power sequencing, noise, ripple, and efficiency.
Ensure power integrity for sensitive ADC and high-speed SerDes subsystems.
Own schematic design and hardware architecture (Xpedition preferred).
Guide PCB layout for high-layer-count, high-speed boards.
Lead design reviews focusing on SI/PI/EMI risks.
Ensure manufacturability (DFM) and testability (DFT).
Lead board bring-up and system integration, including DDR training, PCIe and SerDes link-up, and ADC performance validation.
Debug issues related to signal integrity, jitter and noise, power coupling, and system interaction.
Use lab tools such as oscilloscopes, TDR/VNA, and protocol analyzers.
Work closely with FPGA, firmware, software, mechanical, and system engineering teams.
Align electrical design with system-level performance requirements.
Drive cross-domain trade-offs.
Lead architectural decisions and technical reviews.
Mentor junior engineers in high-speed and mixed-signal design.
Drive structured problem-solving across complex systems.