Electrical Engineer, Senior - Hardware Systems

Positron Corporation•Spokane, WA

About The Position

As a Senior Electrical Engineer at Positron AI, you will be the primary technical authority representing the company as we engage with third-party board manufacturers and ODMs to fabricate our current and future hardware platforms. You will oversee the hardware lifecycle from schematic capture, design validation, and manufacturing–ensuring that the power, thermal, and signal integrity characteristics of our high-performance AI systems meet the demands of HPC environments. This is a high-impact role requiring deep expertise in high-speed communication design and analysis for our Asimov ASIC and the ability to manage complex technical relationships with external partners.

Requirements

BS/MS in Electrical Engineering and 7+ years of experience in high-speed hardware design, signal integrity, power integrity, and board-level system integration.
Proven expertise in SI/PI analysis for ultra-high-speed interfaces (112G SerDes, PCIe Gen 6, and DDR5) and familiarity with advanced PCB materials and/or fine-pitch interposers or package design.
Familiarity with tuning transceiver analog FIR, CTLE, & DFE equalization to compensate for channel loss.
Direct experience managing ODMs or external manufacturing partners through EVT, DVT, and pilot production phases.
Proficiency with industry-standard EDA and simulation tools for SI/PI (e.g., Ansys, Cadence, or Siemens) and hardware debug equipment (e.g., oscilloscopes, logic analyzers).
Strong ability to write clear hardware specifications and communicate trade-offs across ASIC design, firmware, and mechanical/thermal teams.

Nice To Haves

Background in designing carrier boards or add-in cards for AI/ML accelerators.
Experience with collaborating on modeling and analysis CFD/thermal instrumentation and correlating simulations to real-world air-cooled or liquid-cooled performance.
Experience driving hardware through FCC/EMI/EMC, CE, and RoHS/REACH regulatory approvals.
Experience with high-current VRM architectures and transient load-line analysis for large ASICs.

Responsibilities

Act as the primary technical lead and Positron representative for third-party design and build partners during the fabrication of current and future boards.
Perform detailed SI design analysis for 112G PAM4 SerDes communication channels for the Asimov ASIC. Experience with channel simulation is a plus. Specify and review results for a design validation test plan; ensuring robust communication across inter-chip fabrics and external interfaces is achieved for a vast array of physical topologies.
Lead schematic and layout reviews for high-density PCBs (targeting Megtron7, Tachyon100G or similar materials with high layer counts, sequential lamination, buried vias, etc.), including the evaluation of fly-over cable strategies to minimize routing congestion.
Oversee the design of power delivery subsystems, supporting up to 600W TDP, and thermal management strategies to meet air-cooling requirements and performance targets in high-density data center environments.
Own board-level test plan creation and lead the validation of PCIe Gen 6 / CXL link training, transceiver tuning (e.g. CTLE parameters), memory training, and PVT margining and testing.
Manage the hardware risk register, decision logs, and technical escalations with external partners to keep programs on schedule for pilot and manufacturing ramps. Facilitate the transfer of information between internal and external entities, optimizing co-development of package+board for optimal performance.