Senior Director, Hardware Engineering
About The Position
The Senior Director, Central Engineering will lead the development of advanced SoC architecture, modeling methodologies, and design enablement strategies across multiple product lines. The role establishes scalable design and verification methodologies, drives SystemC and SystemVerilog model development, and uses AI-driven techniques to improve productivity, quality, and time-to-market for complex semiconductor SoCs. The position calls for a recognized technical leader with deep expertise in SoC architecture, system modeling, RTL development, and engineering process transformation. The Senior Director partners with product groups, platform teams, and executive leadership to define and deploy next-generation design methodologies that accelerate innovation and enable organizational reuse. The role builds and leads engineering teams, mentors senior technical leaders, and influences long-term semiconductor technology and platform strategy. Renesas describes itself as an embedded semiconductor solution provider with more than 21,000 engineers and problem solvers in over 30 countries. The role is listed as Senior Director in the ENG and Innovation Office/Design Methodology & SoC Architecture function. USA is preferred, and remote work is not available. Employment is regular (PERM), with annual compensation of USD 275,500–344,500.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
- 15+ years of experience in semiconductor or SoC development.
- 8+ years of technical leadership experience managing large engineering organizations and complex programs.
- Proven experience leading SoC architecture, design, or verification teams.
- Strong understanding of SoC architecture and integration, digital design methodologies, IP and subsystem development, hardware/software co-design, and SoC verification methodologies.
- Hands-on experience with SystemC/TLM model development, SystemVerilog and UVM-based verification environments, virtual platforms and executable specifications, SoC performance modeling, and design and verification automation flows.
- Experience creating organization-wide engineering methodologies and design frameworks.
- Demonstrated experience applying AI/ML technologies to semiconductor design workflows.
- Understanding of Generative AI and LLM-based engineering productivity solutions.
- Ability to define and scale AI-driven model development methodologies across multiple teams.
- Strategic thinking with strong execution focus and ability to influence across organizational boundaries.
- Strong mentoring and talent-development skills.
- Data-driven decision-making, a passion for innovation and continuous improvement, and proven ability to lead large-scale engineering transformation initiatives.
- Strong executive communication and stakeholder management skills.
Nice To Haves
- Master's degree or Ph.D.
- Experience leading disruptive methodologies and influencing mindset changes.
- Experience with heterogeneous compute architectures, AI accelerators, MCUs, MPUs, or automotive SoCs.
- Knowledge of cloud-based EDA infrastructure and advanced design automation technologies.
- Track record of driving transformational improvements in engineering productivity and quality.
Responsibilities
- Define and drive the company-wide strategic roadmap for SoC design methodologies.
- Lead architecture reviews and provide technical direction for complex SoC and subsystem development.
- Establish best practices for hardware/software co-design and model-based development.
- Provide technical leadership to cross-functional teams spanning architecture, design, verification, emulation, and software.
- Lead development of transaction-level and architectural models using SystemC/TLM.
- Define methodologies for executable SoC specifications and virtual platforms.
- Align SystemC models, RTL implementations, and software development environments.
- Enable early software development and system validation using virtual prototypes.
- Develop and standardize SoC modeling and verification flows using SystemVerilog, UVM, and related methodologies.
- Promote reusable IP, subsystem, and SoC-level modeling frameworks.
- Drive methodology adoption across product groups to improve predictability, quality, and reuse.
- Establish metrics and KPIs to measure design productivity and model accuracy.
- Define and implement AI-enabled methodologies for model generation, verification, and validation.
- Evaluate and deploy Generative AI, LLMs, and automation technologies to improve engineering efficiency.
- Create AI-assisted workflows for SystemC model generation, SystemVerilog model development, verification content generation, coverage analysis, design documentation, and requirement traceability.
- Lead pilot programs and organization-wide adoption of AI-assisted design methodologies.
- Build and lead high-performing engineering teams.
- Mentor directors, principal engineers, and distinguished engineers.
- Foster collaboration across Central Engineering, Product Groups, and external partners.
- Influence long-term semiconductor technology and platform strategy.
Benefits
- Competitive benefits package alongside salary; further information will be provided during the hiring process.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
