Senior Director, Engineering

Silvaco

About The Position

Silvaco is hiring a Memory Design Lead to drive the architecture, design, customer interface, and delivery of its embedded memory compiler portfolio, including single-port SRAM, ROM, single- and dual-port register files, and dual-port RAM. The role leads a memory design team, sets technical direction across multiple process nodes, and serves as a senior technical voice in customer engagements, from presales architecture discussions through PPA negotiation, integration support, and silicon qualification. It combines technical leadership with direct customer impact, shaping compiler capabilities, PPA competitiveness, and customer SoC integration.

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
10+ years of embedded memory design experience, with production tapeouts of SRAM and at least two of ROM, 1-port register file, 2-port register file, or dual-port RAM.
Deep expertise in bitcell-level circuit design, memory peripherals, self-timed paths, sense amplifier design, and assist circuit techniques.
Hands-on experience across multiple process nodes, including FinFET and/or advanced sub-7nm nodes.
Strong command of SPICE simulation, statistical and Monte Carlo analysis, Vmin/yield modeling, and reliability analysis including BTI, HCI, and EM.
Working knowledge of memory compiler architecture and automation, including assembling instances, generating views, and scaling across configurations.
Hands-on experience with DFT/scan tools such as Tessent or FastScan, power integrity signoff such as RedHawk or equivalent, and layout verification flows including DRC, LVS, and parasitic extraction.
Familiarity with RTL/Verilog modeling of memory compilers, test chip definition and silicon correlation, and SDK/automation development for compiler view generation.
Proven team leadership experience, through direct management or a strong technical lead role, over a team of 6+ memory designers.
Demonstrated success in customer-facing technical roles involving presales, PPA negotiation, and integration support.
Excellent written and verbal communication skills, including presenting complex technical material to engineers, architects, and executives.
Proficiency with scripting languages such as Python, TCL, or Perl, and Linux-based design environments.
Experience working with AI tools such as Claude, OpenAI, or Gemini.
Direct experience interfacing with foundry partners on PDK, bitcell qualification, and reference flow alignment.

Nice To Haves

Prior experience presenting at industry venues such as ISSCC, VLSI Symposium, or custom integrated circuits conferences, or contributing to memory IP standards.
Experience leading memory compiler programs at an IP vendor, foundry, or large semiconductor company.
Background in low-power memory design for mobile, IoT, automotive, or AI/ML accelerator applications.
Experience with multi-port memory architectures beyond 2-port, such as 3-port or 4-port register files, and specialty memories such as TCAM or multi-bank arrays.

Responsibilities

Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM.
Define bitcell selection, peripheral architecture, redundancy and repair strategy, and assist circuits to meet PPA targets.
Optimize Vmin, leakage, performance, area, and yield across PVT corners, process variation, and aging effects.
Own the technical roadmap for the memory portfolio, including compiler variants, process nodes, feature enhancements, and methodology improvements.
Establish design, verification, and signoff methodology; lead design and layout reviews, SPICE/FastSPICE characterization, statistical and Monte Carlo analysis, BIST/repair, DFT, and physical verification.
Lead silicon validation efforts, including test chip development, testing, and reporting.
Lead, mentor, and grow memory design engineers across circuit design, layout, characterization, and compiler/automation.
Set individual and team goals, conduct technical reviews, and develop career paths for engineers at multiple levels.
Allocate engineering effort across roadmap projects, customer commitments, and silicon programs; manage schedules, dependencies, and risks.
Build a culture of design rigor, peer review, and continuous methodology improvement.
Lead presales engagements by qualifying opportunities, presenting Silvaco's memory portfolio, and shaping technical proposals.
Translate customer SoC requirements into compiler specifications and PPA commitments.
Partner with sales, field application engineers, and product management on RFQs, technical evaluations, and competitive benchmarking.
Lead technical workshops with customer architects and design teams, and respond to technical questionnaires and audit-style reviews.
Own PPA analysis across the memory portfolio at instance and SoC-aggregate levels; maintain competitive benchmarks and identify gaps.
Drive what-if and sensitivity analysis to guide architecture trade-offs, and translate PPA insights into customer-ready collateral.
Serve as the primary technical contact for strategic customers from evaluation through integration, tapeout, and silicon validation.
Lead technical reviews, integration debugging, silicon correlation discussions, and root-cause analysis of customer-reported issues.
Coordinate customer issue resolution across design, characterization, CAD, and product teams.
Represent Silvaco in foundry partner meetings and at industry conferences as needed.