Senior Director, AI Interface Architecture

Credo•San Jose, CA

3d•$230,000 - $315,000

About The Position

We are seeking a Senior Director, AI Interface Architecture to solve the system-level interconnection challenges that connect XPUs (NPU/GPU/custom silicon) into working AI infrastructure. This role owns how compute elements are wired, networked, and orchestrated together at node, rack, and cluster scale so that large-scale LLM training and inference run efficiently across the platform.

Requirements

15+ years in systems/interconnect architecture or AI/HPC infrastructure, including 5+ years in a technical leadership role.
Solid understanding of NPU, GPU, and CPU architectures
Strong grasp of DP, TP, PP, EP, and hybrid parallelism strategies and how they drive interconnect and communication patterns.
Familiarity with leading open LLM architectures (e.g., Kimi, Llama, DeepSeek, Mixtral, Qwen) and their impact on system-level communication.
Experience solving rack-, node-, and cluster-scale interconnection and workload-partitioning problems.
Understanding of LLM deployment methods across training and inference from a networking/system-integration perspective.
Strong cross-functional leadership and communication skills.
Bachelor's degree in Computer Engineering, EE, CS, or related field required; Master's or PhD preferred.

Nice To Haves

Experience at a silicon vendor or hyperscaler solving system/network integration for accelerator hardware at scale.
Contributions to open-source AI infrastructure projects (Megatron-LM, DeepSpeed, vLLM, SGLang).
Experience with next-gen interconnect standards (UALink, UEC).

Responsibilities

Own the interconnection architecture linking XPUs across node, rack, and cluster boundaries - not the internal design of the NPUs/GPUs/CPUs themselves.
Solve communication and topology bottlenecks that arise from all kinds of parallelism strategies during distributed LLM training and inference.
Define how the AI software stack (PyTorch, Megatron, DeepSpeed, vLLM, SGLang) interfaces with the underlying interconnect and fabric, ensuring workloads map cleanly onto the network topology.
Work with silicon, networking, and software teams to specify interconnect fabric requirements and resolve integration issues between compute nodes.
Track leading open LLM architectures to anticipate how model structure will stress interconnect and system topology.
Lead and mentor a team of architects focused on system interconnection; represent this strategy to leadership and partners.