Senior Digital Engineer

Renesas Electronics•Chandler, AZ

1d•Onsite

About The Position

Renesas Electronics is seeking a Senior Digital Design Engineer to join its hardware development team in Chandler, Arizona. The role designs power- and area-optimized digital circuits for complex mixed-signal applications, including data conversion and power management products in advanced process nodes. The engineer interprets high-level requirements and architects, designs, and integrates low-power digital circuits, supporting products from concept through mass production in close coordination with the wider organization. The engineer works with Analog, Verification, and Physical Design (P&R) teams to deliver high-quality silicon and meet timing, area, power, schedule, budget, and project deliverable goals. The work spans mixed-signal design flow, including micro-architecture, design partitioning, RTL design, timing constraints, synthesis, timing analysis, LINT, CDC, RDC, UPF, simulation, and coordination of layout. The role also contributes to DFT strategy, verification and test development, behavioral modeling, design documentation and reviews, and silicon evaluation. The engineer may document device errata, develop workarounds, and implement engineering changes as needed.

Requirements

>5 years of digital design experience in wireless handheld, data conversion, or power management.
Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
Fluency in Verilog/SystemVerilog RTL for digital CMOS circuit design.
Strong understanding of ASIC design methodology.
Strong understanding of Lint, CDC, and RDC tools.
Strong understanding of block-level and chip-level verification techniques.
Proven ability to debug RTL and gate-level simulations.
Competence in written and spoken English.
Willingness to travel domestically or internationally on short notice.
Ability to work independently and collaboratively.

Nice To Haves

Experience with mixed-signal design methodologies.
Experience developing design constraints and handing off designs to P&R.
Experience with static timing analysis (STA) and timing closure.
Experience with low-power design techniques, including clock and power gating (UPF).
Experience with power analysis and optimization.
Experience with advanced verification methodologies such as UVM.
Experience with industry-standard protocols such as AMBA or I2C.

Responsibilities

Interpret high-level requirements and architect, design, and integrate low-power digital circuits for mixed-signal data conversion and power management products.
Support the full product lifecycle from concept through mass production, communicating with the wider organization throughout silicon development.
Work closely with Analog and Verification engineers to deliver high-quality silicon solutions.
Help ensure digital development processes meet budget, schedule, and project deliverable goals.
Design digital RTL that meets timing, area, power, and applicable standards specifications.
Integrate designs at the top level and run block-level and top-level simulations.
Participate in mixed-signal design activities, including micro-architecture, design partitioning, RTL Verilog/SystemVerilog design, timing-constraint generation, synthesis, P&R interaction, timing analysis, LINT, CDC, RDC, and UPF.
Work with the P&R team to generate layouts that meet timing, area, and power requirements.
Support DFT strategy and implementation, and review test-case development.
Assist with top-level test-bench debugging and run RTL and gate-level simulations.
Collaborate with analog and digital verification engineers to develop complex pre-silicon verification scenarios.
Support the analog team in developing AMS, SystemVerilog, or Verilog-real behavioral models.
Develop detailed block- and chip-level design documents and collateral.
Lead and participate in key design reviews and complete relevant checklists.
Perform silicon evaluation as required.
Document device errata, develop workaround solutions, and implement engineering changes when necessary.