Senior Digital Engineer

Renesas Electronics • Chandler, AZ

38d • Onsite

About The Position

Renesas Electronics is seeking a skilled and motivated Senior Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications. You will support the full product lifecycle from concept to mass-production, communicating closely with the wider organization through the various stages of silicon development. You will work closely with Analog and Verification engineers to deliver high-quality silicon solutions, ensuring the digital development process is state-of-the-art and achieves budget, schedule, and project deliverable goals. This includes designing digital RTL that meets timing, area, power and any adhering standards specifications, integrating the design at the top level, and running block & top-level simulations. You will participate in all aspects of the Mixed-signal design flow, including Micro-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF. You will also work closely with the P&R team to generate a layout that meets timing, area, and power requirements, support DFT strategy and implementation, and review test case development. Additionally, you will assist with top level test-bench debug, run RTL & gate level simulations, and work with analog and digital verification engineers to develop complex test scenarios for pre-silicon verification. You will support the analog team to develop AMS, SystemVerilog or Verilog-real behavioral models, develop detailed block & chip level design documents and collateral, and hold and participate in key design reviews and completion of various checklists. Finally, you will perform silicon evaluation as required, document device errata, develop work-around solutions, and implement engineering changes when necessary.

Requirements

• >5 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management.
• Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
• Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design.
• Strong understanding of ASIC design methodology.
• Strong understanding of Lint, CDC & RDC tools.
• Strong understanding of block-level & chip-level verification techniques.
• Strong & proven ability to debug both RTL & gate-level simulations.
• Mandatory competence in written and verbal English.
• Willingness to travel domestically or internationally on short notice.
• Ability to work independently and collaboratively.

Nice To Haves

• experience with mixed-signal design methodologies.
• experience developing design constraints and hand-off to P&R.
• experience with STA and timing closure.
• experience with low-power design techniques, including clock and power gating (UPF).
• experience with power analysis and optimization.
• experience with advanced verification methodologies (UVM).
• experience with industry-standard protocols such as AMBA or I2C.

Responsibilities

• Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
• Support full product lifecycle from concept to mass-production; communicating closely with wider organization through the various stages of silicon development.
• Work closely with Analog and Verification engineers to deliver high-quality silicon solutions.
• Ensuring digital development process is state-of-art and achieves budget, schedule, and project deliverable goals.
• Designing digital RTL that meets timing, area, power and any adhering standards specifications.
• Integrating design at the top level and running block & top-level simulations.
• Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF.
• Working closely with P&R team to generate a layout that meets timing, area, and power requirements.
• Support DFT strategy and implementation, and review test case development.
• Assisting with top level test-bench debug, and running RTL & gate level simulations
• Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification.
• Supporting analog team to develop AMS, SystemVerilog or Verilog-real behavioral models.
• Developing detailed block & chip level design documents and collateral.
• Holding and participating in key design reviews and completion of various checklists.
• Perform silicon evaluation as required.
• Document device errata, develop work-around solutions, implement engineering changes when necessary.

Benefits

• Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
• Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure.
• Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior