Senior Digital ASIC Architect

The Charles Stark Draper Laboratory•Cambridge, MA

1d•Onsite

About The Position

A Senior Digital ASIC Architect leads the design of digital integrated circuits from conceptual phases through detailed design, implementation, verification, test and delivery to our customers. The Architect is responsible for developing initial architectural concepts and vetting them through modeling, analysis, and simulation. The Architect works with both Analog and Digital Circuit Designers to identify opportunities for trades across domains which enable the most efficient design solution. The Architect develops top level and circuit-level specifications, develops conceptual circuit designs, reviews detailed block-level designs during implementation, conducts chip level-planning with implementation team, and provides inputs to verification and test planning.

Requirements

Proficiency in integrated circuit design
Understanding of integrated circuits, semiconductors, and general computer architecture
Ability to write detailed design specifications
Ability to manage small technical teams
Excellent verbal and written communication skills
Excellent mathematical skills
Excellent organizational skills and attention to detail
Excellent time management skills with the proven ability to meet deadlines
Strong analytical and problem-solving skills
Ability to prioritize tasks
Demonstrate strong organization, planning, and time management skills to achieve program goals
Requires a bachelor's degree in Engineering, or related field.
Requires 5-7 years of experience with a bachelor's degree, or 3-5 years of experience with a master's degree, or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related.

Nice To Haves

Masters degree preferred.
Proficiency with Cadence or equivalent integrated circuit design tools e.g. Genus, Innovus, Tempus, Voltus
Expertise in high level modeling & mixed-signal verification tools such as System Verilog, SV-RNM, Verilog-AMS
Proficient in scripting for automating aspects of the design, implementation, verification, and test flows.
Experience in top level design for previous tape outs.

Responsibilities

Independently drive integrated circuit-based solutions to complex customer problems.
Develop chip-level integrated circuit requirements based on customer needs.
Design and simulate circuits using functional modeling tools (e.g. MATLAB, Simulink, System Verilog, System C)
Review and mentor individual circuit designers, providing design expertise and conducting requirements adjustments across circuits when necessary
Perform System-on-chip (SOC) design trades between analog, digital hardware, and software implementations to deliver optimized designs.
Evaluate feasibility and costs/benefits of algorithm implementation in hardware vs software.
Participate in top level verification planning with verification team.
Lead multidisciplinary design teams, providing clear and effective communication to the team and project manager.
Participate in technical project planning and provide technical inputs to business development activities.
Deliver presentations of technical solutions to project leadership and customers.
Develop, document, and teach best practices to less experienced engineers.
Develop design documentation, e.g. architectural description, interface definition, and requirements.
Perform other duties as assigned.
Design and simulate circuits at transistor-level to implement architecture and requirement specifications
Contribute to system-level design
Optimize hardware designs for performance, power, and cost
Evaluate the hardware feasibility of complex algorithms and requirements
Independently contribute to complex chip architectures and designs
Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements
Contribute to business development and proposal activities
Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics.