DFX Lead Engineeer

Ericsson • Austin, TX

10d • Hybrid

About The Position

The Senior DFX Lead is the technical owner of Design for Excellence (DFX) and Reliability, Availability and Serviceability (RAS) for one or more ASIC programs at Ericsson. The role defines DFX architecture and test strategy, drives IP- and SoC-level integration with design and physical-design teams, owns test-pattern delivery to test engineering, leads design-side silicon bring-up and yield learning, and carries DFX hooks into in-field test, monitoring and repair. The work spans manufacturing test, Silicon Lifecycle Management (SLM) and in-field RAS, from requirements and architecture through silicon bring-up and field operation. DFX and SLM sign-off is a precondition for tape-out.

The role also shapes SLM architecture and supports runtime applications such as monitoring, diagnostics, telemetry and adaptive power tuning in partnership with systems, firmware and software teams. It advances DFX methodology and automation with EDA vendors and CAD, and mentors DFX engineers while representing DFX to architects, program management and external partners. The position is based in Austin, Texas, with a hybrid, on-site work schedule.

Requirements

• 12 or more years of experience in SoC, IP or ASIC design emphasizing DFX (DFT, DFD or DFM), including several years leading DFX for a complex SoC through tape-out on advanced process nodes.
• Minimum BSEE; MSEE is preferred.
• Expert hands-on command of scan and compression, ATPG, JTAG/IJTAG, boundary scan, and memory and logic BIST, including understanding trade-offs among test quality, test time, area and implementation impact.
• Hands-on experience with a production DFT flow.
• Proven ownership of SoC-level DFT planning, architecture and execution, and DFX verification, including memory BIST, JTAG, boundary scan, in-field tests and custom-IP test interfaces.
• Post-silicon experience in bring-up, yield learning, test-time reduction and pattern delivery, working closely with test and product engineering.
• Working knowledge of RTL (Verilog/SystemVerilog), synthesis, STA, clock and reset design, and physical-design and timing-closure flows.
• Ability to lead through influence, set direction, review others’ work, represent DFX to stakeholders and communicate clearly in writing and verbally across sites and time zones.

Nice To Haves

• Depth in RAS and SLM, including on-die sensors and monitors, fault logging, telemetry, in-field diagnostics, and firmware or SDK that reads them.
• DFT experience for chiplet, 2.5D or 3D designs, such as IEEE 1838.
• System-level test (SLT) methodology and functional ATE pattern enablement.
• Functional-safety or RAS experience on high-reliability products.
• Experience partnering with external ASIC vendors on DFT, test content and test quality.
• Background in wireless infrastructure, networking or compute ASICs.

Responsibilities

• Own DFX and SLM architecture for one or more ASIC programs, including the DFT plan, test strategy and RAS requirements; sign off DFX and SLM scope before tape-out.
• Architect and drive the DFX/SLM stack, including scan and compression, ATPG, memory and logic BIST with memory repair, JTAG/IJTAG and boundary scan, in-field test, and test access for custom, analog and high-speed IP.
• Integrate DFX into RTL at IP and SoC level, own DFX timing constraints (SDC), and partner with physical design on implementation and timing sign-off.
• Define and execute RTL and gate-level verification of DFT, debug and lifecycle-monitoring infrastructure for production-test and in-field use cases, including DFT rule checks and equivalence checking.
• Deliver test content to test engineering and silicon partners, including pattern generation, fault simulation, structural, at-speed and functional coverage closure, and test-time optimization; review test quality against DPPM targets with ASIC vendors.
• Define on-die debug and observability features, including scan or array dumps and register-state snapshots on functional failure; lead design-side bring-up, yield learning and failure analysis, and feed findings into subsequent tape-outs.
• Shape SLM architecture with the SLM team and enable runtime applications such as in-field monitoring, diagnostics, telemetry and adaptive power tuning with systems, firmware and software teams.
• Work with EDA vendors and CAD to define next-generation DFT flows and automate the DFX execution pipeline across programs.
• Mentor DFX engineers, review their work, and represent DFX to architects, program management and external partners across Austin, Sweden and partner sites.

Benefits

• Competitive compensation package and opportunity for annual short-term variable compensation bonus.
• Choice of three medical plan options and a dental plan option, with company credits toward premiums for employees and eligible covered dependents.
• Ericsson US 401(k) Plan with an automatic 3% company contribution and matching contributions of up to 4% when the employee contributes at least 5% of eligible pay.
• Company credits toward basic life insurance, accidental death and dismemberment coverage, and short- and long-term disability coverage.
• Option to participate in Ericsson’s Stock Purchase Plan.
• Minimum 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time and 80 hours of sick time annually; paid time off is prorated based on start date.
• Up to 16 weeks of paid maternity leave and 6 weeks of paid parental or adoption leave at 100% of pay.
• Financial wellness programs, educational assistance, matching gifts and recognition programs.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior