Senior DFX Engineer

Ericsson•Austin, TX

3d•Hybrid

About The Position

The Ericsson Radio and Baseband Products have our ASICs as their backbone, and our challenge is to design and deliver those so that our technology leadership position in the market accelerates. Our ASICs are challenging when considering the overall combination of Size/complexity, Test Quality & Reliability, Power, Performance targets, advanced process node technology, multi-die integration, and pushing the design methodology on an ongoing basis. We are looking for a DFX Engineer to join our established & very experienced DFX & SLM team (Silicon Lifecycle Solutions), the technical authority for DFX and Silicon Lifecycle Management across Ericsson Silicon. With production silicon in the field and multiple ASIC programs in active development, the team owns DFX/SLM from chip specification through tape-out sign-off to years of in-field operation. The role covers all aspects of DFX and SLM (Architecture, Design, Verification, Methodology, Production Test, Silicon Debug, In-field Test & Telemetry). It includes working closely with other functions within Austin and in Sweden, and with our ASIC and EDA partners, as the design takes shape at the IP, SOC, and system level to ensure that the final ASIC achieves the program goals.

Requirements

5+ years of experience working in SOC/IP/ASIC design team with an emphasis around DFX (DFT/DFD/DFM). Experience on DFX Verification specifically (Verification of features like: Memory BIST, JTAG, Boundary Scan, In-field Tests, Custom IP Test Interface etc.) would be of great interest for this role.
Minimum Education: BSEE
Must have working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency, and their impact to overall design implementation.
Experience with SOC level DFT planning, architecture, and execution.
Exposure to Silicon Lifecycle Management: in-field/in-system test, telemetry-driven monitoring and diagnostics, and RAS concepts. Familiarity with IEEE 1149.1, 1687, and 1838 is a plus.
Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function.
Experience applying AI/ML to engineering workflows (debug, triage, data analysis, flow automation), or a demonstrated drive to build it into daily execution.
Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with Test & Product Engineering teams for long term strategic improvements.
Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come.
Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs.

Nice To Haves

Familiarity with IEEE 1149.1, 1687, and 1838 is a plus.

Responsibilities

Strengthen a world-class DFX & SLM group and its role as the technical authority for silicon lifecycle management
Strategize, architect, plan, design/implement & verify DFT and SLM capability across multiple ASIC programs, from chip specification to tape-out sign-off
Extend our silicon lifecycle capability in the field: in-system test, silicon telemetry, monitoring, diagnostics, and repair
Partner with Test Team to define overall Test Strategy
Partner with Physical Design teams (IP & SOC) to develop complex SOCs
Work closely with EDA Vendors, ASIC partners & CAD team to define next generation DFT/SLM flows and methodology with latest & greatest features
Apply AI as a first-class tool in daily execution: automating flows, accelerating debug and triage, and extracting insight from silicon and system telemetry
Mentor & coach junior engineers within the team and helping them achieve their goals
Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams

Benefits

Choice of three medical plan options
Dental plan option
Company credits towards medical and dental premiums
Ericsson US 401(k) Plan with automatic 3% company contribution
Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay
Company credits for basic life insurance and basic accidental death and dismemberment coverage
Company credits for short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time
80 hours of sick time annually
Up to 16 weeks of paid maternity leave
6 weeks of parental or adoption leave at 100% of pay
Financial wellness programs
Educational assistance
Matching gifts
Recognition programs