Senior DFX Engineer

Ericsson•Austin, TX

3d•Hybrid

About The Position

The Senior DFX Engineer will join Ericsson’s established DFX and Silicon Lifecycle Solutions (SLM) team, which serves as the technical authority for DFX and silicon lifecycle management across Ericsson Silicon. The team supports ASICs from chip specification through tape-out sign-off and years of in-field operation. The role spans DFX and SLM architecture, design, verification, methodology, production test, silicon debug, in-field test, and telemetry. The engineer will work with teams in Austin and Sweden, as well as ASIC and EDA partners, across IP, SoC, and system levels to help ensure ASICs meet program goals. The position is hybrid, with on-site work in Austin, Texas, and is not remote. The engineer will help plan and deliver DFT and SLM capabilities across multiple ASIC programs, extend lifecycle capabilities in the field, collaborate on test strategy and SoC development, and improve DFT/SLM flows and methodology. Applying AI to everyday engineering work—including automation, debug, triage, and analysis of silicon and system telemetry—is part of the role. The position also includes mentoring junior engineers and working effectively across sites and geographies. Ericsson describes its compensation package as including a salary range determined by factors such as location and job-related qualifications, skills, and experience, plus eligibility for an annual short-term variable compensation bonus. Benefits include medical and dental plan options, 401(k) contributions and matching, basic life and accidental death and dismemberment coverage, short- and long-term disability coverage, and an employee stock purchase plan. Time off includes accrued vacation, personal days, annual holidays, volunteer time, and sick time. Paid leave includes up to 16 weeks of maternity leave and 6 weeks of parental or adoption leave at 100% of pay. Other company-paid benefits include financial wellness programs, educational assistance, matching gifts, and recognition programs.

Requirements

At least 5 years of experience working in a SoC, IP, or ASIC design team with an emphasis on DFX, including DFT, DFD, or DFM.
BSEE minimum education requirement.
Working knowledge of DFX standards and practices, ATPG, scan, JTAG, iJTAG, and BIST, including trade-offs involving test quality, test time, efficiency, and design implementation.
Experience with SoC-level DFT planning, architecture, and execution.
Good focus on automation and infrastructure to support an efficient DFX execution pipeline.
Experience applying AI/ML to engineering workflows such as debug, triage, data analysis, or flow automation, or demonstrated drive to incorporate it into daily work.
Experience with post-silicon debug, yield bring-up, test-time and pattern delivery, and collaboration with Test and Product Engineering teams.
Understanding of physical design implementation flows and methods to support smooth DFT integration and efficient, high-quality handoffs.

Nice To Haves

Experience in DFX verification, especially verification of Memory BIST, JTAG, Boundary Scan, in-field tests, or custom IP test interfaces.
Exposure to Silicon Lifecycle Management, including in-field or in-system test, telemetry-driven monitoring and diagnostics, and RAS concepts.
Familiarity with IEEE 1149.1, IEEE 1687, and IEEE 1838.

Responsibilities

Strengthen the DFX and SLM group and its role as the technical authority for silicon lifecycle management.
Strategize, architect, plan, design, implement, and verify DFT and SLM capabilities across multiple ASIC programs from chip specification through tape-out sign-off.
Extend in-field silicon lifecycle capabilities, including in-system test, silicon telemetry, monitoring, diagnostics, and repair.
Partner with the Test Team to define the overall test strategy.
Partner with Physical Design teams at IP and SoC levels to develop complex SoCs.
Work with EDA vendors, ASIC partners, and the CAD team to define next-generation DFT/SLM flows and methodology using current features.
Apply AI in daily work to automate flows, accelerate debug and triage, and extract insights from silicon and system telemetry.
Mentor and coach junior engineers and help them achieve their goals.
Collaborate with cross-site and cross-geography teams to build effective working relationships and deliver efficiently across teams.
Support post-silicon debug, yield bring-up, test-time and pattern delivery, and long-term strategic improvements with Test and Product Engineering teams.
Continuously improve flows, methodology, and architecture to enable the team to scale.
Integrate DFT smoothly into physical design implementation and enable efficient, high-quality handoffs.

Benefits

Annual short-term variable compensation plan with an opportunity for a bonus, subject to eligibility and payout rules.
Choice of three medical plan options and a dental plan option; company credits cover the cost Ericsson pays toward eligible medical and dental premiums.
401(k) plan with an automatic 3% company contribution and matching contributions of up to 4% when eligible employees contribute at least 5% of eligible pay.
Basic life insurance and basic accidental death and dismemberment coverage.
Short-term and long-term disability coverage.
Employee Stock Purchase Plan.
At least 15 days of accrued vacation for new employees, prorated based on start date.
Up to 3 personal days per year.
11 annual holidays.
8 hours of volunteer time.
80 hours of sick time annually.
Up to 16 weeks of paid maternity leave.
6 weeks of parental or adoption leave at 100% of pay.
Financial wellness programs.
Educational assistance.
Matching gifts.
Recognition programs.