Senior DFT Engineer

NVIDIA•Us, CA

2d•Hybrid

About The Position

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. You will have the chance to define, prototype and deploy next generation DFX architectures and methodologies across all our products. This includes high speed test access architectures, the in-system-test architecture, ISO26262 functional safety diagnostic for in-field testing and beyond, silicon debug & bring-up, productization, and silicon life-cycle management among others. As a member on our DFX Architecture team, your responsibility will be to craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms etc. Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI, SW development, and Operations teams to productize new methodologies. Help the team with delivering efficient workflows and tools to help productize these features on industry's leading processors for deep learning, gaming, HPC and supercomputing. You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

Requirements

BSEE (or equivalent experience) with 8+ years, MSEE with 5+ years of experience or PhD with 3+yrs in DFT or related domains.
Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation.
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Strong programming and scripting skills in Perl, Python or Tcl desired.
Extraordinary written and oral communication skills with the curiosity to work on rare challenges.

Responsibilities

Implement state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
Develop and deploy DFT methodologies for next generation products.
Define, prototype and deploy next generation DFX architectures and methodologies across all products.
Craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms.
Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI, SW development, and Operations teams to productize new methodologies.
Deliver efficient workflows and tools to help productize these features on industry's leading processors for deep learning, gaming, HPC and supercomputing.
Mentor junior engineers on test designs and trade-offs including cost and quality.