Senior Development Test Engineer — Pre & Post-Silicon Software Test, Validation and Characterization

TYLsemi•San Jose, CA

3d•$180,000 - $216,000

About The Position

We are seeking an experienced individual to own the end-to-end testing, characterization, and failure analysis strategy for complex, next-generation multi-die packages. The role involves owning the complete validation lifecycle across a multi-die architecture, covering high-speed die-to-die (UCIe) interconnects, Power Delivery Networks (PDN/PMIC), Platform Management Controllers (PMC), and PCIe/CXL subsystems. Additionally, the position requires applying statistical analysis and machine learning to test data for outlier detection, bench-to-ATE correlation, and predictive telemetry signals, while emphasizing physical root-cause analysis over ML model reliance.

Requirements

8–10+ years in post-silicon validation, system software testing, silicon bring-up, or development test for complex SoCs / ASICs / GPUs.
Advanced proficiency in C and Python for low-level bare-metal test content, hardware abstraction, and automation frameworks.
Proven experience with Shmoo plotting PVT corner testing, jitter/margin analysis, and guard-band definition.
Hands-on experience building or executing error-injection and recovery validation campaigns on production silicon.
Fluency with oscilloscopes, protocol analyzers (PCIe/CXL), logic analyzers, BERTs, thermal chambers, controllable power supplies, and JTAG debuggers.
Practical, protocol-level understanding of high-speed serial interfaces (PCIe, CXL, or UCIe) and control buses (I2C, SPI, UART, PMBus, SMBus).
Solid grasp of system power delivery—including sequencing, PMIC telemetry, DVFS, voltage regulation, and protection trip limits.
Competency with toolchains (Git, CMake, GCC/Clang, CI pipelines) and statistics/data analysis over test populations.
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
AI coding and automation tool usage is a must for this role.

Responsibilities

Define development test strategies, coverage targets, content architecture, and strict traceability from architectural requirements to validation evidence.
Write low-level C and Python test suites, including bare-metal exercisers, traffic generators, stress patterns, and custom firmware drivers/hooks.
Build robust test frameworks featuring instrument control, automated sequencing, structured result capture, and Hardware-in-the-Loop (HIL) CI/CD integration for continuous validation.
Develop lab-to-ATE correlation test suites and drive smooth handoffs to Product & Test Engineering (PTE).
Own the development test plan, including coverage goals, content architecture, and the traceability between a requirement, the test that exercises it, and the evidence it passed.
Build minimally invasive fault-injection hardware/software infrastructure that perturbs target datapaths without destabilizing the test setup.
Execute rigorous error campaigns targeting CRC retries, lane degradation/repair, sideband timeouts, PCIe AER, DMA/IOMMU translation faults, and PMIC reset conditions.
Validate system firmware error handlers, watchdog timers, and hardware-level fault containment behavior under out-of-spec conditions.