Senior Design Verification Engineer

Astera Labs•San Jose, CA

2d•$148,500 - $165,000

About The Position

As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. This role offers the opportunity to own meaningful verification challenges within CCE2, from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs’ hyper-growth mission by helping deliver highly reliable PCIe and UALink connectivity products that keep AI accelerators, memory, and compute resources operating at scale.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
2–5 years of experience in design verification for complex ASICs or SoCs.
Hands-on experience with SystemVerilog and UVM-based verification environments.
Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
Familiarity with simulation, waveform-debug, regression, and coverage tools.
Strong debugging, communication, and collaboration skills in a fast-paced product development environment.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience verifying PCIe, UALink, UCI, or other high-speed connectivity and switching protocols.
Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.
Experience with Python, Perl, or Tcl for verification automation and regression infrastructure.
Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity.

Responsibilities

Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.
Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.
Review designs and verification plans with architecture and RTL teams to identify corner cases early.
Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models.
Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCI behavior.
Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.
Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones.
Develop regression strategies and automation to improve test quality, turnaround time, and failure triage.
Partner with design and post-silicon teams on issue isolation, root-cause analysis, and silicon bring-up readiness.