Senior Design Verification Engineer

Hewlett Packard Enterprise • Sunnyvale, CA

1d • Hybrid

About The Position

We are seeking a motivated and detail-oriented Senior Design Verification Engineer to join our team. This is an entry-level position ideal for recent graduates who are passionate about hardware design verification and eager to build a career in the semiconductor or systems engineering industry. As a Design Verification Engineer, you will work alongside experienced engineers to verify the correctness and functionality of digital designs. You will develop testbenches, write test plans, debug failures, and contribute to improving our verification methodologies. This is an excellent opportunity to apply your academic foundation to real-world challenges in a collaborative, fast-paced environment.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science from an accredited institution.
• Coursework or academic projects in one or more of the following: Digital logic design and computer architecture.
• Hardware Description Languages (HDL) such as Verilog or VHDL.
• Basic understanding of verification concepts (simulation, assertions, code coverage).
• Familiarity with at least one programming or scripting language (e.g., Python, C, C++, or SystemVerilog).
• Strong analytical and problem-solving skills.
• Effective written and verbal communication skills.
• Ability to work collaboratively in a team environment.

Nice To Haves

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Academic or class projects involving networking protocols (e.g., Ethernet, TCP/IP, USB, PCIe) or communication protocols (e.g., UART, SPI, I2C, AXI, AMBA).
• Hands-on experience with SystemVerilog and UVM (Universal Verification Methodology) through coursework or personal projects.
• Exposure to constrained-random verification, functional coverage, and assertion-based verification techniques.
• Experience with EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Familiarity with scripting for automation (e.g., Python, Tcl, Perl, Shell).
• Coursework or project experience in any of the following areas: FPGA prototyping and implementation.
• SoC (System-on-Chip) design and integration.
• Signal processing or embedded systems.
• Contributions to open-source hardware projects or participation in relevant competitions (e.g., IEEE, ACM).
• Coursework or project experience involving AI/ML applications such as Gen AI, using AIML chatbot as a programming aid, etc.
• Internship or co-op experience in a design verification or related role.

Responsibilities

• Develop testbenches
• Write test plans
• Debug failures
• Contribute to improving our verification methodologies

Benefits

• Health & Wellbeing: comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• Personal & Professional Development: specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• Unconditional Inclusion: unconditionally inclusive in the way we work and celebrate individual uniqueness.
• Flexibility to manage our work and personal needs.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level