Design Verification Engineer

Redolent • Folsom, CA

3d • Onsite

About The Position

We have the following urgent requirement with our client: Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs. Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required.

Requirements

• Strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench
• Usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs
• Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
• Strong understanding of different phases of ASIC and/or full custom chip development is required

Nice To Haves

• Verification experience AXI, NoC, HBM, DDR4, PCIe verification is a plus
• Verification experience in full chip verification is a plus
• Experience in modeling SystemC and using SystemC based models in verification is a plus
• Experience with FPGA programming and software is a plus
• Verification experience in PCIe, Processors, Graphics is a plus
• Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
• Some DFX/DFT and UPF/power-aware-simulation experience is a plus

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed