Design Verification Engineer

Redolent•Menlo Park, CA

3d•Onsite

About The Position

One of our direct clients is urgently looking for a Design Verification Engineer in Menlo Park, CA. This role requires a strong understanding of verification methodologies and experience in debugging simulation failures to guide digital design.

Requirements

BSEE/MSEE/BSCompE/MSCompE with 5 years of industry experience.
3+ years of UVM experience.
3+ years of SystemVerilog experience.
Deep understanding of coverage, constrained-random, and transaction level verification.
Experience with Verdi/VCS is a must.
Experience with test plan documentation.
Familiarity with Python3/Bash/Tcl scripting is a must.
Experience with debugging simulation failures to guide digital design.
Experience with fixed-point arithmetic.

Nice To Haves

BSEE/MSEE/BSCompE/MSCompE with 10 years of industry experience.
Experience with performance analysis and performance characterization is a plus.
Experience with using a Hierarchical Verification Plan is a plus.
Experienced with a full ASIC/SOC tape out from beginning to end.
Experience with video processing or graphics pipelines is a plus.
Experience with floating-point arithmetic in addition to fixed-point arithmetic.

Responsibilities

Develop and execute verification plans.
Utilize UVM and SystemVerilog for verification.
Implement coverage, constrained-random, and transaction-level verification strategies.
Debug simulation failures and guide digital design engineers.
Document test plans.
Utilize scripting languages for automation and support.
Experience with fixed-point arithmetic.
Experience with performance analysis and characterization.
Experience with a Hierarchical Verification Plan.
Experience with a full ASIC/SOC tape out from beginning to end.
Experience with video processing or graphics pipelines.
Experience with floating-point arithmetic in addition to fixed-point arithmetic.