Senior Bring up Methodology Lead

NVIDIA•Santa Clara, CA

5d•$196,000 - $368,000•Hybrid

About The Position

NVIDIA Silicon Codesign Group is seeking a versatile engineer to join the HW bring-up methodology team. The SCG team is uniquely positioned to have an end-to-end view of the product development cycle - from early architecture definition, through bringup, to product release.

Requirements

MS in Engineering or related field, or equivalent experience.
10+ years of experience leading complex, multi-site technical programs in semiconductor, SoC, or system/platform development.
Proven experience influencing decisions and leading multi-functional teams in a fast-paced, highly technical environment.
Background in silicon or system bringup.
Strong leadership and problem-solving skills with the ability to think strategically about end-to-end silicon solution readiness and tactically about day-to-day execution.
Enthusiastic, responsive, and passionate about process improvement, with a track record of identifying gaps and driving better methodologies.
Excellent communication and interpersonal skills; able to align diverse collaborators and drive clear, timely decisions.

Nice To Haves

Hands-on experience with first-silicon bringup, post-silicon validation, or silicon debug for complex chips and or systems.
Experience driving transitions from NPI to HVM, including readiness criteria, sign-off processes, and ramp optimization.
Familiarity with lab operations, validation infrastructure, and common tools used in hardware bringup.

Responsibilities

Led end-to-end planning and on-time execution of Nvidia's new chip bringup effort, from pre-silicon through production deployment.
Coordinate multi-functional teams across Architecture, Build, Validation, DFT, SW, System, and Operations to drive shared bringup achievements.
Improve cross-team communication, work, and handoffs.
Develop and standardize methodologies, processes, and workflows for silicon bringup, creating reusable checklists and playbooks.
Drive scheduling, equipment, and material logistics to support ambitious NPI and production schedules.
Lead post-action reviews and convert learnings into concrete process improvements for future silicon and solution bringups.
Contribute to post-silicon learnings that feed back into architecture, design, and pre-silicon validation to improve the next generation.
Serve as the central point of contact for bringup timeline status, risks, and mitigations for leadership.