Senior ASIC Verification Engineer - HSIO

NVIDIA•Westford, MA

1d•$136,000 - $264,500

About The Position

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of the next generation of High Speed I/O controllers for the world’s leading SOCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”

Requirements

Bachelors or Masters Degree (or equivalent experience) with 5+ years of relevant experience
Experience at Unit/Sub-system/SOC level and expertise in SystemVerilog, UVM
Expertise in comprehensive verification of IP or interconnect protocols (e.g. Ethernet, USB, SATA)
Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies (UVM) and exposure to industry standard verification tools for simulation
Excellent debugging, analytical, and problem solving skills
Great communication and collaboration skills to interact within the team and across functional teams

Nice To Haves

Good understanding of the system level architecture of HSIO-based designs, like Ethernet or CXL
Experience with Perl, Python or similar scripting and/or SW programming languages is highly desireable
Experience with AI-enabled code assist or root-cause analysis tools

Responsibilities

Be responsible for the verification of ASIC design, architecture, golden models and micro-architecture of High Speed I/O controllers, like Ethernet and NVLink, at IP/sub-system levels using advanced DV methodologies such as UVM.
Building reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
Understanding the design specification and implementation, defining the verification scope, developing test plans, tests, and the verification infrastructure used to verify the correctness of the design.
Collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.