Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
About The Position
As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
Requirements
- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
- 5+ years of experience in processor or other related high-performance semiconductor designs.
- Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required.
- Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
Nice To Haves
- Experience in interconnect/cache/core design is desirable.
- Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
Responsibilities
- Synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches.
- Evaluate the physical design for next-generation Nvidia coherent interconnects and system-level caches.
Benefits
- equity
- benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
