Senior ASIC DFT DV Engineer (Hybrid)

Cisco•San Jose, CA
•$167,700 - $245,200•Hybrid

About The Position

The Senior ASIC DFT DV Engineer will verify Design-for-Test (DFT) architecture supporting ATE screening, in-system testing, debugging, and diagnostics. The role owns the MBIST methodology across the Silicon One portfolio and establishes unified, high-quality memory-testing standards. It also involves architecting reusable, hierarchical infrastructures that scale across large designs and help accelerate time-to-market for future silicon. The engineer works with front-end RTL and backend physical design teams to understand chip architecture and drive high-quality DFT verification. This is a hybrid role requiring three days per week at Cisco’s San Jose location. The application window is expected to close on 11/12/2026.

Requirements

  • Bachelor’s degree in Electrical Engineering or equivalent with at least 7 years of experience, or a master’s degree with at least 4 years of experience.
  • Prior experience with test planning based on complex design specifications.
  • Experience debugging using DVE or Verdi.
  • Prior experience with memory architectures such as SRAM and DRAM, and their failure modes.
  • Experience with TCL, Python, or Perl.

Nice To Haves

  • Experience in Verilog or SystemVerilog.
  • Experience addressing memory failure correlation in production.
  • Experience in silicon testing and Automatic Test Equipment (ATE).
  • Experience with industry-standard DFT tools such as Synopsys DesignWare, SMS, TestMax, or Mentor Graphics Tessent.

Responsibilities

  • Plan tests and develop test benches to verify DFT architecture for ATE screening, in-system testing, debugging, and diagnostics.
  • Own the MBIST methodology across the Silicon One portfolio and drive unified, high-quality memory-testing standards.
  • Architect reusable, hierarchical infrastructures that scale across large designs and accelerate time-to-market for future silicon.
  • Work with front-end RTL and backend physical design teams to understand chip architecture and drive high-quality DFT verification.

Benefits

  • Medical, dental, and vision insurance.
  • 401(k) plan with Cisco matching contribution.
  • Paid parental leave.
  • Short- and long-term disability coverage.
  • Basic life insurance.
  • Restricted stock unit grants may be available to eligible employees, subject to continued employment and vesting terms.
  • Paid holidays and, for non-exempt employees, a floating holiday.
  • Paid day off for employee’s birthday.
  • Paid year-end holiday shutdown.
  • Paid personal wellness days.
  • Vacation time or flexible vacation time off, depending on employee classification and eligibility.
  • Sick time off.
  • Additional paid time away may be requested for critical or emergency family issues.
  • Optional paid volunteer days.
  • Annual bonuses may be available for non-sales roles, subject to Cisco policies.
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