The Senior ASIC DFT DV Engineer will verify Design-for-Test (DFT) architecture supporting ATE screening, in-system testing, debugging, and diagnostics. The role owns the MBIST methodology across the Silicon One portfolio and establishes unified, high-quality memory-testing standards. It also involves architecting reusable, hierarchical infrastructures that scale across large designs and help accelerate time-to-market for future silicon. The engineer works with front-end RTL and backend physical design teams to understand chip architecture and drive high-quality DFT verification. This is a hybrid role requiring three days per week at Cisco’s San Jose location. The application window is expected to close on 11/12/2026.
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Job Type
Full-time
Career Level
Senior