Senior ASIC Design Verification Engineer - Terawave

BLUE ORIGIN • Los Angeles, CA

4d • $230,398 - $322,557

About The Position

The ASIC Verification Engineer leads verification of complex digital subsystems for next-generation Satellite communication ASICs. This role requires strong expertise in advanced verification methodologies, architecture understanding, and multi-functional collaboration to ensure robust, high-quality silicon.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC verification experience.
• Deep hands-on expertise in System Verilog and UVM.
• Strong understanding of verification planning, assertions, and coverage closure.
• Experience verifying complex digital control and datapath logic.
• Proven debugging capability across RTL, testbench, and system interactions.
• Ability to work effectively across multidisciplinary engineering teams.

Nice To Haves

• Background in Space based communications, wireless communications, or modem/baseband hardware.
• Experience verifying LDPC/BCH/FEC blocks, framing engines, beamforming logic, or DSP pipelines.
• Familiarity with formal verification tools and methodologies.
• Experience with low-power verification, CDC/RDC verification, or reset-domain behavior.
• Knowledge of high-speed interface verification and hardware/software interactions.

Responsibilities

• Lead verification planning and execution for complex blocks or subsystems.
• Develop sophisticated UVM environments, reference models, scoreboards, protocol monitors, and assertions.
• Translate architecture and design specifications into comprehensive verification strategies and measurable coverage goals.
• Drive functional coverage closure, regression health, and verification signoff readiness.
• Identify verification gaps, corner cases, and high-risk scenarios early in the development cycle.
• Collaborate closely with design, systems, DFT, firmware, and physical design teams.
• Review testbench architecture, stimulus quality, and debug methodologies for technical excellence.
• Mentor junior engineers in verification standard processes.
• Support bring-up, emulation, prototyping, and post-silicon debug activities as needed.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior