Senior ASIC Design Engineer - Terawave

Blue Origin • San Diego, CA

3d

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. The Senior ASIC Design Engineer leads the design of complex digital IP or subsystems for advanced Satellite communication ASICs. This role requires strong technical depth in RTL design, subsystem architecture, and multi-functional execution to deliver robust, high-performance silicon for space and ground communication platforms.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 5–8+ years of ASIC digital design experience.
• Proven experience owning large blocks or subsystems in ASIC or FPGA development.
• Strong expertise in System Verilog/Verilog RTL design and debug.
• Working knowledge of synthesis, STA concepts, CDC/RDC, and integration flows.
• Experience balancing PPA tradeoffs in production-quality designs.
• Demonstrated ability to work across multidisciplinary teams.

Nice To Haves

• Background in Space based communications, wireless communications, or digital modem architecture.
• Experience with channelization, beamforming, synchronization, equalization, or coding engines.
• Familiarity with radiation-tolerant or high-reliability design considerations.
• Experience with formal verification, low-power methodologies, or emulation/prototyping.
• Knowledge of high-speed interface design and data movement architectures.

Responsibilities

• Lead the design and delivery of complex ASIC IP or subsystems from specification through RTL release.
• Define microarchitecture for high-speed, power-efficient digital signal-processing and control logic.
• Drive IP or subsystem trade studies involving throughput, latency, area, power, reliability, and schedule.
• Collaborate with systems, algorithm, and architecture teams to translate communication requirements into hardware implementations.
• Partner with verification, DFT, physical design, and firmware teams to ensure successful integration and tape-out readiness.
• Review RTL, test plans, and implementation results to maintain high design quality.
• Identify and mitigate technical risks early in the development cycle.
• Mentor junior engineers and help establish standard processes in coding, review, and debug.
• Support post-silicon bring-up and root-cause analysis of lab or field issues.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior