Senior ASIC Design Engineer, Low Power AI

Qualcomm•Markham, ON

10d•CA$104,900 - CA$154,900

About The Position

Qualcomm Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC; a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues. As we deliver to the premium tiers of the mobile, compute, automotive, and IoT markets, we strive to pioneer new and/or improved functionality and innovate to minimize power consumption. Make a difference, join a team on the cutting edge and become an integral part of Qualcomm’s growth and momentum. We are looking for an ASIC Design Engineer that will work with industry leading edge HW Design technology and processes and provide expertise for next generation initiatives. As a leader in delivering ultra-low power solutions, there will also be an emphasis on power analysis and optimization. This is a replacement position.

Requirements

2+ years of professional industry ASIC hardware design and/or implementation experience.
Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
Understanding of ASIC/VLSI concepts
Experience in logic synthesis using Synopsis and/or Cadence tools.
Ability to work legally in Canada
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ years of ASIC design, verification, or related work experience.
OR PhD in Science, Engineering, or related field.

Nice To Haves

Experience with power analysis, power modeling and low power RTL design.
Experience with clock domain crossing techniques
Power and performance experience with an audio IP core, DSP, various audio interfaces (I2S, PCM, SLIMbus, SoundWire, Audio Codec) and accelerators (low-power AI/ML inference).
Experience with a subset of DC, FC, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre, etc.)
Experience with design rule check (Spyglass, etc.), Formal verification (Formality, LEC, etc.) and/or Power analysis and simulation
Scripting skills (Python , PERL, TCL or C)
Knowledge of bus interface protocols (APB, AHB, AXI)
Experience with post-silicon debug
Experience with UVM
C coding

Responsibilities

Develop micro-architecture and module specifications for digital audio and AI IP blocks including those that interface with the SoC
Implement modules and sub-systems and integrate IP from other teams in Verilog RTL
Analyze performance, area, power, and system cost tradeoffs for different implementations
Review opportunities for power optimization for ultra-low power designs
Power projection activities, what/if scenario exploration
Work with the design verification team to debug tests at the module, sub-system and SoC levels throughout the ASIC development cycle (pre and post-silicon)
Work with the implementation team to review synthesis results, review power metrics and reach static timing closure
Analysis with silicon debug team to correlate stated objectives for both function and power