Low Power Design/Methodology Engineer

Qualcomm • San Diego, CA

6d • $115,600 - $173,400

About The Position

This role involves the design of adaptive power management controllers, on-chip sensor controllers, and digital power meters. The engineer will perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Collaboration is key, working closely with technology/circuit design teams to meet IP block specifications, and with verification/physical design teams for IP implementation. The position also supports SoC teams in integrating low power/power management IP solutions into wireless SoC chips and front-end design flows, and works with system/software/test teams to enable low power and functional safety features in wireless and automotive SoC products, respectively. A significant part of the role includes creating and enhancing low power methodologies across the entire design cycle (RTL to GDS), analyzing the impact of new methodologies, and providing feedback on chip and system architecture. The engineer will also perform and understand block and chip-level power analysis and create block-level power models.

Requirements

• 3 years of experience doing low power digital ASIC design.
• Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
• Familiar with scripting languages like Python, Perl, TCL
• Understanding of electrical engineering concepts, circuit analysis and logic design skills.
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Nice To Haves

• Previous experience in AVS (adaptive voltage scaling) desired.
• Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high speed clocking desired.
• Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.
• Good understanding of SoC architecture/micro-architecture.
• Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus.
• Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.

Responsibilities

• Design adaptive power management controller, on-chip sensor controller and digital power meter.
• Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
• Work closely with technology/circuit design team to close IP block specification/requirement.
• Work closely with verification/physical design team to complete the IP design implementation.
• Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows.
• Work closely with system/software/test team to enable the low power feature in wireless SoC product.
• Work closely with system/software/test team to enable functional safety feature in automotive SoC product.
• Create/Enhance low power methodologies covering entire design cycle from RTL to GDS.
• Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues.
• Provide feedback for low-power chip and system architecture.
• Understand and perform block & chip-level power analysis.
• Understand and create block-level power models.
• Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level