Low Power Design Methodology and Optimization Engineer

Google•Austin, TX

3h•$192,000 - $278,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in CPU low power design and optimization.
Experience with low-power design (e.g., dynamic and leakage, power estimation, and optimization), data analytics, and profiling.
Experience in flow automation (Python, C, C++).

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in RTL design and low-power design techniques.
Experience with power management and DVFS.
Experience with CPU benchmarking, performance analysis, and industry study.
Experience with vendor tools such as PTPX, Ansys Power Artist, and Synopsys Prime Power RTL.
Knowledge of CPU microarchitecture.

Responsibilities

Develop and implement advanced low power design methodologies for CPU architectures.
Perform detailed power analysis, estimation, and optimization across various design stages.
Collaborate with RTL design, verification, and physical design teams to integrate power-saving features.
Drive the adoption of innovative power reduction techniques and tools.
Contribute to the definition and validation of power management specifications.