Senior ASIC Design Engineer - DFX

NVIDIA•Us, CA

About The Position

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You’ll help drive innovation across the full silicon lifecycle—from pre-silicon to post-silicon—while mentoring and collaborating with cross-functional teams.

Requirements

Bachelors degree (or equivalent experience) with 8+ years of experience, or Master’s degree in Electrical Engineering or related field with 6+ years experience.
5+ years of hands-on experience in SoC architecture, RTL design, and verification.
Strong proficiency in micro-architecture and RTL development using Verilog.
Deep expertise in DFT design, methodology, and implementation.
Familiarity with related domains such as clocking, STA, place & route, and power optimization.
Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.
Proficiency in scripting languages such as Python, Perl, or Tcl.
Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges.

Nice To Haves

UVM experience is a plus.

Responsibilities

Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
Define and align feature sets by working closely with architects, platform, and software teams.
Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
Create and execute test plans to support both functional and DFT full-chip verification.
Support post-silicon bring-up and validation efforts including debug and issue resolution.
Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.