Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

Qualcomm • Markham, ON

14d • CA$124,200 - CA$174,200

About The Position

Be part of the group that is working on technology that will bring “Cognition” to all connected devices: That means devices that don’t just react to their surroundings, they interact with the world. We are a compact, tightly knit ASIC IP team of architects, design, and verification engineers. We create HW IP in the heart of the Snapdragon DSP Neural Processing Unit (NPU) that works in coordination with the other NPU components to accelerate AI machine learning, video and other dsp applications. We’re continuously evolving and improving our design and verification architectures to tackle complex engineering problems. To achieve the high standards of Qualcomm products, our team members contribute with a variety of skills and participate in many aspects of the design, verification, and final product evaluation processes. We are looking for few good ASIC Design Engineers to be part of our team to innovate and design leading edge Qualcomm Snapdragon DSP processors that will empower AI and video processing applications and products. We are open to all levels of applicants, the role (Jr, Sr., Staff) and responsibility will be commensurate with experience.

Requirements

• Strong problem solving and analytical thinking skills
• First-time-right hardware requires an attention to detail and careful planning
• Excellent communication skills
• Self-motivated, goal oriented, team player
• Bachelors - Engineering, Computer Engineering
• Understanding of digital logic
• some design experience, whether in work, co-op, or coursework
• 2+ years of direct experience in ASIC design, debug verification, synthesis, SystemVerilog, design tools (Synopsys, Cadence, Mentor) and flows
• Understand high performance processor design for high speed and low power
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

• Design high speed, high bandwidth, low power digital hardware solutions using SystemVerilog
• Take on the challenge of achieving the high performance goals of the product while minimizing power and area
• Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision
• Contribute to definition, micro-architecture and documentation of HW IP
• Collaborate closely with the Verification team to test and debug new HW IP
• Collaborate closely with the Verification team to close coverage on new HW IP
• Create assertion based models for functional and formal verification using SystemVerilog
• Create functional coverage models using SystemVerilog
• Evaluate synthesis results to verify the design meets the speed, power and area targets
• Support internal hardware integration SW teams around the world
• Support internal software teams during their application testing
• Collaborate with software teams to develop new features
• Use of various design tools (VCS Simulator, Synopsys Compiler , Linting, CDC, LEC, CLP etc.) to check and improve design quality
• Provide ideas and further the innovation of ASICs, IP cores, and process flows

Benefits

• competitive annual discretionary bonus program
• opportunity for annual RSU grants
• highly competitive benefits package is designed to support your success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level