Senior Analog/RF System Architect

Black Semiconductor

About The Position

We are seeking a skilled Senior Analog/RF System Architect at Black Semiconductor to own the analog, RF, and high-speed SerDes architecture of the CMOS SoCs powering our graphene photonic interconnect technology. You will define the electrical architecture at the boundary between electronics and photonics, including PLLs, TIAs, drivers, equalizers, ADC/DACs, and CDRs, translating system-level performance targets into scalable and manufacturable SoC solutions. Working closely with the Photonics Circuit Designer, Package Electrical/SI Architect, analog design, and digital/EIC teams, you will drive architecture decisions across the complete electrical-to-optical channel. You will own system-level trade-offs across bandwidth, power, reach, cost, and manufacturability, while engaging directly with customers and product teams to translate deployment requirements into architectures and evaluate the impact and ROI of future features.

Requirements

Ph.D. in Electrical Engineering or a related discipline with 5+ years of relevant experience, or a Master's degree with 8+ years of relevant experience (or equivalent demonstrated impact).
Proven experience owning high-speed SerDes and analog/mixed-signal system architectures, including PLLs, TIAs, drivers, equalizers, ADC/DACs, and CDRs for 56G/112G/224G+ PAM4 systems in advanced CMOS technologies (FinFET/GAA).
Strong system-level architecture experience, including taking heterogeneous SoCs from concept through architecture sign-off, ideally involving advanced packaging technologies such as 2.5D/3D integration.
Expertise in electrical-optical link budget analysis, including transmitter impairments, channel loss, reflection, crosstalk, and receiver noise considerations.
Hands-on experience characterizing high-speed analog/RF designs using modern lab equipment, including BERTs, high-speed oscilloscopes, and VNAs.
Strong understanding of high-speed interconnect standards, including PCIe, UCIe, and CXL, and their influence on analog/RF architecture decisions.
Ability to collaborate across domains, working closely with photonic circuit designers, package engineers, digital designers, product teams, and customers to resolve complex architecture trade-offs.
Strong technical communication skills, with the ability to translate customer deployment requirements into architecture specifications and communicate complex design decisions across technical and business stakeholders.
Experience with analog/mixed-signal design, system modeling, and architecture tools, including Cadence Virtuoso/Spectre, MATLAB/Simulink, Keysight ADS, HSPICE, Ansys HFSS/SIwave, Python-based modeling and automation workflows, and high-speed lab measurement environments.

Nice To Haves

Experience with silicon photonics or electro-optic interface design
Analog design team leadership
System-level SerDes/optical link modeling
Semiconductor product development including reliability and qualification requirements

Responsibilities

Own the analog/RF and high-speed SerDes architecture for optical transceiver SoCs, defining solutions for drivers, TIAs, equalizers, ADC/DACs, PLLs, and CDRs targeting 112G/224G+ PAM4 and next-generation interconnects.
Define and maintain Analog Product Requirement Specifications (PRS) per product, including architecture, verification plans, and performance, power, and area (PPA) estimates.
Drive system-level link budget closure across the complete electrical-to-optical channel, accounting for transmitter impairments, channel loss, reflection, crosstalk, and receiver noise for Integrated Graphene Photonics (IGP)-enabled optical links.
Own the Analog IP roadmap, aligning architecture direction with technology capabilities, EDA flows, and contractor/external design partnerships.
Partner with the Photonics Circuit Designer, Package Electrical/SI Architect, and SoC design teams to reconcile analog/RF architecture decisions with PIC layout, package electrical constraints, and system requirements.
Define Customer Requirement Documents (CRDs) for customer engagements and collaborate directly with customers to ensure architecture choices meet deployment requirements.
Lead SoC concept and feasibility studies by exploring architectural options, driving system-level trade-offs, recommending final architectures, and supporting product teams in modeling use cases and ROI for candidate architectural features.
Track and incorporate relevant interconnect standards, including PCIe, UCIe, CXL, and emerging die-to-die and optical standards, into architecture decisions.