Senior Analog Design Engineer

Ciena • Ottawa, ON

29d

About The Position

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track-record of success over 30-years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions. To further strengthen our team, we are looking for a hardworking senior analog design engineer who will be involved leading design of advanced high-speed analog circuits in the latest deep-submicron CMOS technologies. Your role as a senior analog designer will be to architect and deliver advanced high-speed circuits within a larger team who are responsible for a full mixed signal IP block solution that will be integrated into the Wavelogic family of products. These analog macros include design and delivery of electrical interface-facing DAC and ADC based SERDES solutions for 224G and 448G, optical-line-facing high-speed DAC and ADC circuits interfacing with optical modulators and detectors, low-jitter high-speed PLL circuits, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions, etc. In this role: You will be responsible to perform feasibility work with various circuit topologies to recommend the best solution to carry through implementation by weighing tradeoffs and discussing these with other members of the team including system groups to guide formation of a circuit requirement specification. You will be responsible for the complete and detailed design of the analog blocks assigned to you including close collaboration with analog layout team members and more junior members of the design team as applicable who may assist with some aspects of the overall implementation through to full GDSII delivery to Ciena’s integration partner. Reporting on status updates on a regular basis, participation in team meetings and sharing of experience with the rest of the group. Characterization in Ciena’s state-of-the art lab of the analog circuits from test-chips through to full product implementation working with members of our Analog Macro Integration team.

Requirements

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc, MEng/MSc, or Ph.D level.
• Experience leading designs in advanced CMOS technology with a minimum of 5-years industrial experience.
• A highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically address sophisticated technical problems
• Excellent organization, written and oral (English) interpersonal skills
• Proficiency above the intermediate level with use of applicable design tools from Cadence, Mentor and Synopsys for analog design (eg Virtuoso, Calibre, STAR-RC, MMSIM).
• A history of successful analog circuit product deliveries.

Nice To Haves

• Experience with 2.5D or 3D E-M tools such as HFSS or EMX
• Experience with team-leadership within an analog macro design group
• Architect or System Design experience for complex analog macro IP solutions using tools such as MatLab and/or C++
• Experience with mixed-signal design validation using state-of the art probing and test equipment

Responsibilities

• Perform feasibility work with various circuit topologies to recommend the best solution to carry through implementation by weighing tradeoffs and discussing these with other members of the team including system groups to guide formation of a circuit requirement specification.
• Responsible for the complete and detailed design of the analog blocks assigned to you including close collaboration with analog layout team members and more junior members of the design team as applicable who may assist with some aspects of the overall implementation through to full GDSII delivery to Ciena’s integration partner.
• Reporting on status updates on a regular basis, participation in team meetings and sharing of experience with the rest of the group.
• Characterization in Ciena’s state-of-the art lab of the analog circuits from test-chips through to full product implementation working with members of our Analog Macro Integration team.

Benefits

• Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.
• We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level