Senior AI Systems Architect/Researcher

Intel Corporation•Santa Clara, CA

2d•$195,200 - $275,580•Onsite

About The Position

The Central Engineering Group Networking Architecture Group defines next-generation networking silicon and platform architecture for hyperscale data centers, cloud infrastructure, and AI workloads. Its focus includes IPU/DPU platforms, advanced packet processing, programmable networking, and data-movement technologies for distributed computing systems. This senior AI systems architecture and research role translates communication, memory, and orchestration bottlenecks in large-scale AI into networking architecture, IP, and platform direction. The role works across research, architecture, silicon, software, and product teams to shape distributed AI infrastructure and influence N+1 to N+3 product roadmaps. The architect will define how AI systems move data at scale across xPUs, DPUs, IPUs, NICs, memory, and heterogeneous storage; develop architectural approaches; and translate research insights into network architecture and software capabilities. The position calls for systems-level reasoning across interconnect, memory hierarchy, software runtime, and compute, as well as maintaining substantial knowledge of state-of-the-art principles and theories, contributing regularly to scientific literature and the research community, and potentially participating in IP development.

Requirements

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with at least 5 years of relevant experience; or a PhD in one of these fields or a related STEM field with at least 2 years of relevant experience.
Experience with modern AI training and/or inference systems, including model architecture internals, hardware algorithm code design, serving runtimes, and large-scale memory and data-movement bottlenecks.
Hands-on experience with modern inference and training serving stacks such as vLLM or SGLang, including practical understanding of disaggregated prefill/decode, model parallelism, tensor parallelism, and their communication patterns.
Experience in computer architecture and system-level design, focused on networking, interconnect, or memory subsystems.
Proficiency in C/C++ and/or Python.
Architectural vision across AI systems, networking, memory, and software domains.
Ability to influence and align multiple teams and disciplines without authority.
Systems thinking across compute, memory, network, and software.
Sound decision-making under ambiguity and incomplete data.
Ability to build cross-functional relationships and translate workload needs into architectural innovation.
Ownership and accountability for driving initiatives end-to-end.
Ability to stay current with evolving AI systems, inference runtimes, interconnects, memory technologies, and cloud infrastructure trends.

Nice To Haves

Experience with memory hierarchy and system bottleneck analysis, including caches, memory controllers, bandwidth/latency tradeoffs, and the memory wall in data-intensive workloads.
Experience with high-performance networking and data-movement technologies such as RDMA/RoCE, InfiniBand, or equivalent transport and interconnect.
Experience with IPU/DPU/SmartNIC or accelerator-centric SoCs, particularly in cloud and hyperscale environments.
Familiarity with PCIe, CXL, and memory semantics for high-performance I/O.
Experience defining architecture from concept through silicon, platform software, or shipping product, including translating workload analysis into architecture requirements and new IP.
A track record of cross-team technical leadership and influencing architecture and roadmaps at a senior level.

Responsibilities

Analyze real AI serving and training workloads, identify communication and memory bottlenecks, and translate findings into new IP, offload engines, platform features, and architecture requirements.
Drive hardware-software co-design across compute, DPU/IPU, NIC, SoC fabric, and AI serving runtimes, reflecting networking and data-movement capabilities in frameworks such as vLLM and SGLang.
Define architectural direction for data movement at scale across xPU-to-xPU, xPU-to-storage, and cross-node paths spanning IPU/DPU platforms, NICs, and heterogeneous storage.
Shape next-generation packet processing, RDMA-class transport, and programmable networking IP for hyperscale AI inference and training.
Investigate data-movement bottlenecks in large-scale AI and Agentic inference and training, including KV-cache transfer, disaggregated prefill/decode, model and tensor parallelism, and communication collectives, and translate findings into architectural requirements.
Reason across the memory hierarchy and interconnect to minimize copies, latency, and bandwidth overhead while balancing latency-sensitive control paths and bandwidth-intensive data paths.
Shape multi-generation compute, memory, and interconnect roadmaps across IPU/DPU product lines, defining scaling strategies, migration paths, and architecture requirements.
Align architecture across networking, SoC fabric, firmware/OS/drivers, and performance modeling teams.
Contribute regularly to scientific literature and the research community, and potentially participate in development of Intellectual Property.