Senior AI SoC Design Engineer

Intel CorporationSanta Clara, CA
$164,470 - $311,890Onsite

About The Position

Join Intel's AI Revolution. Intel's new AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware. This role is at the heart of Intel's product development process, combining technical expertise, creative problem-solving, and disciplined execution. By joining our team, you will work alongside some of the brightest minds in the industry to define and build next-generation computing platforms that enable transformative experiences for billions of users worldwide.

Requirements

  • RTL design, coding, and simulation using SystemVerilog.
  • Microarchitecture and SoC architecture.
  • System-level design principles like power, performance, and area trade-offs/optimizations.
  • 7+ years of experience with a Bachelor's degree, 5+ years with a Master's degree, or 3+ years with a PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Nice To Haves

  • Passion for continuous learning, including an understanding of AI models and how they shape AI hardware architectures
  • Proven ability to effectively communicate across multidisciplinary teams
  • Track record of disciplined execution and delivering high-quality designs under tight deadlines
  • Proficiency in implementing clock, reset, power domain crossings both logically and physically
  • Experience in driving innovative solutions to complex design challenges

Responsibilities

  • Define microarchitecture and implement RTL for SoC blocks
  • Collaborate with IP providers to integrate IPs into the SoC
  • Collaborate with verification and firmware teams to meet functional and performance goals
  • Own design quality including clock/reset/power domain crossings and timing constraints
  • Collaborate with physical design teams to meet timing/area/power goals
  • Drive high-quality design handoffs to partner teams (verification, physical design, firmware, packaging)
  • Contribute to next-generation architecture discussions

Benefits

  • competitive pay
  • stock bonuses
  • health
  • retirement
  • vacation
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