Semiconductor Device Modeling Engineer

Intel•Phoenix, CA

2d•Hybrid

About The Position

The Compact Device Modeling Group (CDMG) is part of Intel's Design Enablement (DE) organization. DE is a key pillar in enabling Intel to deliver design, development, and manufacturing services that allow internal and external customers to bring winning products to the marketplace. Your work will directly enable design teams to get to market faster with leadership products based on innovative technologies. As a member of CDMG, you will be at the forefront of co-optimizing Intel's state-of-the-art process technology, enabling customers with diverse design needs to deliver best-in-class products for data-centric applications. As a Semiconductor Device Modeling Engineer, you will be responsible for characterizing device behavior and generating/updating device models for new technologies while ensuring robust and accurate model simulations.

Requirements

Master's degree in Electrical Engineering or a related discipline with a minimum of 3+ years of industry experience in the semiconductor field; OR PhD in Electrical Engineering or a related discipline with a minimum of 1 year of industry or research experience and a dissertation focused on semiconductor devices or processes.
Hands-on experience in Python or C, Shell programming.
Experience or course work in semiconductor device physics, process flow, layout and simple circuit design and simulation.
The ability to work independently after the initial ramp-up time.

Nice To Haves

Ph.D. degree in electrical engineering or related discipline with 3 + years of industry experience in the semiconductor field.
Experience in BSIM models and other compact models, extraction tools (ICCAP or MBP), and commercially available simulators. (example: HSPICE, SPECTRE, etc.)
Understanding of corner, statistical and sub-circuit models and their usages.
Understanding of layout effects and models.
Understanding of basic analog and digital circuit blocks and model interaction.
Hands-on experience in semiconductor device DC/CV characterization tools, techniques, and systems.
Experience in test automation and RF/noise/reliability tests is a plus.
Understanding of Aging Simulations and reliability methodologies and tools is a plus.
Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions.