RTL Design Engineer

Teradyne•North Reading, MA

About The Position

Teradyne is a global test and automation specialist, providing sophisticated solutions for next-generation technologies. Their test technology ensures electronic devices work correctly, and their automation solutions help manufacturers develop and deliver products efficiently. Teradyne fosters a positive and inclusive work environment, valuing diversity and innovation. The Silicon Technology Engineering (STE), Digital ASIC Group at Teradyne is responsible for developing advanced node ASICs for next-generation products like SOC and Memory Test Instruments. This role involves joining a best-in-class Digital team as an RTL Designer, collaborating with an Analog team and product architects to develop Teradyne’s next generation large Mixed Signal ASICs. The position covers all phases of development, including specification, architecture, design, verification, physical design, and silicon bringup, utilizing cutting-edge AI tools for productivity.

Requirements

BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
Extensive logic design experience writing RTL in Verilog
Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT
Experience with logic synthesis and timing constraints
Experience with clock domain crossings (CDC) and static timing analysis (STA)
Experience with high speed memory and serial
Experience with automation through scripting such as Python, Tcl & Make

Responsibilities

Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect
Integration of industry standard and Teradyne custom IPs
Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
Providing timing constraints and STA support to the Physical Design team through timing closure
Providing post silicon lab bringup and debug support