RF Frequency Synthesis Architect

Tacit•San Francisco, CA

1d•$150,000 - $200,000•Onsite

About The Position

We are seeking an RF Frequency Synthesis Architect to design and advance our next generation RF signal synthesis architectures. The ideal candidate has strong expertise in PLLs, synthesizers, oscillators, LO generation, phase-noise optimization, and low-power frequency-generation techniques, with experience spanning RFIC, package, module, and integrated RF hardware platforms.

Requirements

Master’s degree or PhD in Electrical Engineering, RF Engineering, Microwave Engineering, or related field.
5+ years of experience in RF frequency synthesis, or advanced RF system design.
Strong understanding of: Frequency synthesis architectures, PLL and VCO design, Oscillator theory, RF/microwave fundamentals, Phase-noise and jitter optimization
Experience with RF design and simulation tools such as: ADS, Cadence, AWR, LTspice, CST or HFSS.
Experience with RFIC/IC design and SoC, package, module, or dense RF hardware integration.
Strong analytical, debugging, and system-level problem-solving skills.

Nice To Haves

Experience with alternative frequency-generation techniques beyond conventional PLL-based synthesis, including injection-locked oscillators (ILO), digitally assisted synthesis, DDS-based approaches, Delay-Line oscillator, open loop, oscillator-based, ADPLL/DCO architectures, or hybrid frequency-generation techniques.
Experience with radar, sensing technologies, or mixed-signal systems.
Experience developing novel RF architectures or advanced low power wide band signal-generation techniques.
Publications, patents, or research contributions related to RF frequency synthesis or oscillator technologies.

Responsibilities

Design and develop power efficient advanced RF frequency synthesis architectures.
Improve phase noise, jitter, spurs, harmonics, frequency stability, spectral purity, and power efficiency.
Evaluate and compare PLL, VCO, DCOs, oscillator, LC resonator and alternative frequency-generation approaches across power, phase noise, tuning agility, integration complexity, and scalability.
Conduct RF simulation, modeling, and system-level tradeoff analysis.
Support architecture selection, component evaluation, debugging, validation, and prototype integration.
Guide implementation across RFIC, package, laminate, module, and dense RF hardware integration environments.
Collaborate with RF, hardware, firmware, and systems teams to optimize RF performance.