ML Augmented IC Design Engineer

Qualcomm•Santa Clara, CA

1d•Onsite

About The Position

We are seeking a highly skilled RF/Analog IC Design Engineer with working knowledge of Machine Learning to join our team in Santa Clara. This role is ideal for candidates with strong hands-on RFIC / analog circuit design expertise who also have practical experience applying ML techniques to engineering problems. The work involves designing and developing complex radio frequency integrated circuits in complex SoC’s and discrete RFIC’s. Perform radio signal path and circuit topology analysis and detailed transistor-level design of highly integrated transceivers and associated blocks for wireless applications, 4G, 5G, WLAN, BT and GPS standards using advanced process technologies. Utilize complex analysis, simulation, engineering, science and mathematical principles to compose ML algorithm structures to solve problems. Debug and assess performance of algorithms in actual application hardware. This position requires expertise in both RFIC design and ML to be considered. While RF/Analog IC design is the primary focus of this role, the ability to leverage ML for design optimization, modeling, analysis, and automation is essential.

Requirements

Master’s or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
Strong, proven experience in RF/Analog IC circuit design (this is mandatory).
Working knowledge of machine learning, demonstrated through practical application to engineering problems.
Proficiency with RFIC design tools and simulation environments.
Proficiency in Python and familiarity with common ML frameworks (e.g., PyTorch, TensorFlow, or equivalent).
Strong analytical, problem-solving, and debugging skills.
Ability to communicate complex technical concepts clearly in both written and verbal form.
Bachelor's degree in Electrical Engineering with 3+ years of experience with designing RF/Analog circuits for wireless products (e.g., LNA's, PLL's) and 2+ years of ASIC design, verification, or related work experience.
OR Master's degree in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience.
OR PhD in Electrical Engineering or related field.
2+ years of academic or professional experience using two or more of the following software: CADENCE, Virtuoso, ADS.

Nice To Haves

Experience applying ML to circuit design, modeling, optimization, or EDA workflows.
Exposure to hardware-aware or resource-constrained ML models.
Experience working with real silicon data and closing the loop between ML predictions and measured results.
Familiarity with industry trends in ML-assisted circuit design or automation.

Responsibilities

Define, design, and develop complex RF and analog integrated circuits for highly integrated SoCs and discrete RFICs.
Perform transistor-level design, signal-path analysis, and circuit topology development for wireless applications (4G, 5G, WLAN, BT, GPS).
Independently derive circuit-level specifications from system-level requirements.
Develop and analyze RF architecture and critical building blocks using advanced RFIC design methodologies.
Run and analyze complex simulations across PVT, mismatch, and stress conditions.
Collaborate closely with layout engineers on floor planning, layout review, and physical verification.
Review test plans, analyze silicon/test results, and drive root-cause analysis and fixes.
Contribute to next-generation RFIC architecture and technology direction discussions.
Apply machine learning techniques to RF/analog design problems such as modeling, prediction, optimization, or design-space exploration.
Develop or use ML models (e.g., regression models, neural networks, decision trees, autoencoders, or related approaches) for circuit performance prediction or analysis.
Collaborate with cross-functional teams to integrate ML-driven insights into RFIC design workflows.
Analyze datasets generated from simulations, measurements, or silicon to improve design decisions.
Document ML methodologies and clearly communicate results to RF and system design teams.