Research Aide - XSD - Cantoro, Federico - 5.27.26

Argonne National Laboratory•Lemont, IL

2d•Onsite

About The Position

This project will support the design and simulation of silicon quantum dot devices using a CMOS-compatible process framework informed by GlobalFoundries 22FDX fabrication rules. The research aide will investigate device geometries, electrostatic confinement, and tunability of quantum dot structures through numerical modeling and layout-aware design. The goal is to identify practical device architectures that are compatible with advanced semiconductor fabrication constraints while maintaining the electrostatic control needed for quantum applications. Silicon quantum dots are promising building blocks for quantum information science because they can leverage the mature silicon manufacturing ecosystem and offer potential advantages in scalability and integration. However, high-performance quantum dot devices require careful balancing of competing constraints: gate geometry, dielectric stack design, charge confinement, tunnel barrier control, and manufacturability within foundry design rules. Modern simulation tools enable rapid exploration of these design spaces before fabrication. By modeling electrostatics, charge accumulation, confinement potentials, and sensitivity to process constraints, one can evaluate which layouts are most likely to produce functional devices in a practical CMOS platform.

Requirements

Currently enrolled in undergraduate or graduate studies at an accredited institution.
Graduated from an accredited institution within the past 3 months; or Actively enrolled in a graduate program at an accredited institution.
Must be 18 years or older at the time the appointment begins.
Must possess a cumulative GPA of 3.0 on a 4.0 scale.
If accepting an offer, candidates may be required to complete pre-employment drug testing based on appointment length.
Must complete a satisfactory background check.

Responsibilities

Develop an understanding of silicon quantum dot device operation and key design parameters.
Construct and evaluate simulation-ready device geometries consistent with 22FDX-inspired design and layout constraints.
Study how gate dimensions, layer thicknesses, spacings, and bias conditions influence quantum dot formation and tunability.
Compare candidate device layouts for their ability to support: single-dot or double-dot formation, controllable tunnel barriers, charge sensing integration, compatibility with scalable fabrication approaches.
Help generate design recommendations for future prototyping and fabrication.