Regional Graduate Program - Engineer Verification and Validation

Infineon•Andover, MA

8d•$65,000 - $90,000•Hybrid

About The Position

Infineon is seeking a talented individual with a good understanding of analog circuit design to drive the analog behavioral modeling role and to become an integral part of the Infineon R&D team. The successful candidate will join a dynamic team of designers, chip architects, and systems engineers to develop leading-edge high-performance power management solutions for the computing market. This role is part of a two-year Graduate Program involving training rotations across divisions, working with multiple managers, and travel to various U.S. locations. The program aims to develop future leaders within Infineon.

Requirements

BSEE, BSME, or equivalent with 1+ years of relevant verification experience
Proficient with Cadence Virtuoso, ADE Explorer, Xcelium, and Spectre simulation flows
Experienced in Verilog-AMS/SystemVerilog and AMS behavioral modeling practices
Comfortable scripting in Python, and/or C/C++ for automation and data parsing
Familiar with Unix/Linux command line, editors, and version control systems
Strong debugging skills, effective cross-functional communication, and ability to work independently and in teams
Experience using bug tracking systems and maintaining reproducible simulation regressions
Willingness to travel ~20% for the RGP role for a two year period, then return to either Andover MA, Raleigh NC, or Austin TX at the end of the program

Responsibilities

Develop new strategies that leverage AI to aid in the improvement of the verification flow and translates to faster iteration cycles, better coverage testing, higher quality documentation, and overall product successes
Generate Verilog-AMS and SystemVerilog behavioral models and correlate results with schematic-level performance using targeted testbenches
Develop mixed-signal simulation workbenches in Cadence ADE Explorer and Xcelium and automate regression runs
Create schematics, produce schematic netlists for simulation, and maintain hierarchy configurations for tool flows
Verify device-level and system-level requirements through simulation, interpreting results and documenting discrepancies
Contribute to verification of DFT plans, digital scan support, ATE preparation, and bench testability assessments
Debug analog and digital integration issues and drive resolution with design and test teams
Coordinate with design, test, and production teams to support pre-silicon verification and production IC validation
Participate in training rotations across 2–4 divisions, work with multiple managers, and travel to various U.S. locations as needed for a two year period
Create and present progress PowerPoint updates for the program, product demonstrations (if applicable) for internal and external teams as needed
Mentor future RGP members during your last year as a RGP (roughly 1 hour per month during active mentoring periods)