This position is responsible for, but not limited to, the following job duties: Work as part of a physical design team implementing chips from netlist to GDSii with good understanding of the technology elements as well as design flow in all stages. Responsible for floorplanning, design partition and block pin assignment. Perform blocks PnR, timing closure, physical verification. Perform blocks IR/EM analysis. Experience with chip level IR/EM analysis is a big plus. Familiar with scripting languages such as tcl, perl and python. Write scripts to automate physical design flow and make it more efficient. Expertise on low power IC design is desirable. Good knowledge on physical verification using Mentor’s Calibre tool.
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Job Type
Full-time
Career Level
Senior