R&D Engineer IC Design 5

Broadcom•San Jose, CA

15h•$143,800 - $230,000

About The Position

This individual will be a key member of the ASIC system-level verification team. Responsibilities include developing complex verification environments, creating comprehensive test plans, and verifying high-performance network switch ASIC/FPGAs. The role involves hands-on implementation across every aspect of ASIC verification while collaborating closely with system architects, design engineers, and verification teams. The ideal candidate will have a proven track record of completing multiple successful ASIC design and verification cycles—from architecting testbenches (networking background preferred) to achieving full verification closure.

Requirements

8+ years of ASIC design/verification experience
Complete understanding of Verilog design
Hands-on experience with C/C++
Strong working knowledge of object-oriented programming (OOP)
Strong working knowledge of modern ASIC verification flows (e.g., UVM/SystemVerilog)
Complete mastery of Verilog for simulation
Familiarity with ASIC design flows for deep sub-micron technologies
Must have completed multiple ASIC tape-outs, with at least one project taken from initial concept through full production
Fully comfortable with technical and business English across documentation, cross-functional collaboration, and executive communications

Nice To Haves

Networking background preferred for architecting testbenches
Experience with networking protocols (e.g., Ethernet, PCIe, routing/switching)

Responsibilities

Developing complex verification environments
Creating comprehensive test plans
Verifying high-performance network switch ASIC/FPGAs
Hands-on implementation across every aspect of ASIC verification
Collaborating closely with system architects, design engineers, and verification teams