Qubit Control Physical Design Engineer

Intel•Hillsboro, OR

17d•Hybrid

About The Position

As a Qubit Control Physical Design Engineer, you will drive or participate in the following: Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals. Will be responsible for block-level physical design delivery along with closure of backend flows, electrical requirements and improving silicon yield. Will work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in cryogenic control design. Will drive physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. Will work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA. Contribute to developing physical design methodologies.

Requirements

Bachelor’s, Master’s, or Ph.D. degree, with 8+ years of relevant experience.
Qualified experience may have been gained through professional employment, academic institutions, research activities, university projects, coursework, or other comparable educational and professional endeavors.
Experience with logic design and digital circuits.
Experience in Python, PERL/TCL, Linux/Unix shell and C.

Nice To Haves

Experience in low power, high frequency physical design techniques leveraging advanced syn/PnR tool features, and best in class physical design methodology.
Experience using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with timing budgeting, floor-planning, physical integration, and verification to converge complex designs.
Knowledge in deep sub-micron technology, along with its implications to timing, power, and area.
Excellent communication and interpersonal skills.
Ability to work independently and/or lead a physical design partition in collaboration with cross functional teams.
Experience with DFT and DFM flows.
Ability to provide mentorship, guidance to junior engineers and be a very effective team player.

Responsibilities

Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals.
Responsible for block-level physical design delivery along with closure of backend flows, electrical requirements and improving silicon yield.
Work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in cryogenic control design.
Drive physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.
Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA.
Contribute to developing physical design methodologies.