Sr. Principal Product Engineer

Cadence Systems•San Jose, CA

10h

About The Position

This position presents an exciting opportunity within Cadence’s Digital and Signoff Group (DSG) for a Product Engineer. In this dynamic environment, you’ll collaborate closely with R&D, Application Engineering & product marketing teams to help drive the development of advanced chip design software tools. As a Product Engineer, you will serve as a key technical resource, providing place-and-route expertise to both Cadence customers and internal development teams. Candidates should bring a strong motivation and energy, along with a thorough understanding of ASIC design methodologies across all stages of the RTL to GDSII flow. Hands-on experience with timing closure and PPA optimization at 7nm and below is essential. Your analytical strengths will be vital in diagnosing customer challenges and delivering well-organized solutions. Excellent communication skills are required to ensure clear and effective collaboration.

Requirements

BS in Electrical Engineering with at least three years of experience, or an MS in Electrical Engineering with a minimum of one year in digital implementation as either a design or product engineer
Solid understanding of VLSI physical design and timing analysis, including familiarity with clock tree synthesis, routing optimization, and silicon signoff challenges
Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below nodes is required
Strong verbal and written communication skills