Sr. Principal Product Engineer

Cadence Design SystemsSan Jose, CA

About The Position

This position offers an exciting opportunity within Cadence’s Digital and Signoff Group (DSG) for a Product Engineer. In this dynamic environment, you will collaborate closely with R&D, Application Engineering, and product marketing teams to drive the development of advanced chip design software tools. As a Product Engineer, you will serve as a key technical resource, providing place-and-route expertise to both Cadence customers and internal development teams. Candidates should possess strong motivation and energy, along with a thorough understanding of ASIC design methodologies across all stages of the RTL to GDSII flow. Hands-on experience with timing closure and PPA optimization at 7nm and below is essential. Your analytical strengths will be vital in diagnosing customer challenges and delivering well-organized solutions. Excellent communication skills are required to ensure clear and effective collaboration. Cadence is a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable customers to create revolutionary products and experiences. Cadence is recognized by Fortune Magazine as one of the 100 Best Companies to Work For, known for its empowering culture and dedication to pushing the limits of the industry.

Requirements

  • Strong motivation and energy
  • Thorough understanding of ASIC design methodologies across all stages of the RTL to GDSII flow
  • Hands-on experience with timing closure and PPA optimization at 7nm and below
  • Analytical strengths in diagnosing customer challenges and delivering well-organized solutions
  • Excellent communication skills
  • BS in Electrical Engineering with at least three years of experience, or an MS in Electrical Engineering with a minimum of one year in digital implementation as either a design or product engineer
  • Solid understanding of VLSI physical design and timing analysis, including familiarity with clock tree synthesis, routing optimization, and silicon signoff challenges
  • Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below nodes
  • Strong verbal and written communication skills

Nice To Haves

  • Proficiency in scripting languages or AI tools for productivity enhancement

Responsibilities

  • Supporting Cadence’s digital products
  • Tracking and resolving customer issues alongside R&D and release teams
  • Conducting design benchmarks
  • Developing innovative flows and methodologies tailored to customer needs

Benefits

  • Paid vacation
  • Paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • A variety of medical, dental and vision plan options
  • Incentive compensation: bonus
  • Incentive compensation: equity
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