Product Development/DFX Lead - Neuromorphic Computing

Intel Corporation•Austin, TX

1d•$141,910 - $269,100•Hybrid

About The Position

For nearly a decade, Intel's Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach. Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators. If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads. We are seeking a senior product development engineer to lead the DFT/DFX strategy for Intel's neuromorphic silicon program. This role offers a unique opportunity to help define manufacturing and test methodologies for groundbreaking computing architectures that push beyond the limits of traditional AI systems. As the DFT/DFX lead in Intel's neuromorphic silicon team, you will architect and drive innovative test, debug, and reliability solutions that enable high-quality, high-volume production. Loihi's use of asynchronous circuits and advanced integration technologies presents challenges that cannot be addressed by conventional DFX approaches, creating opportunities to develop new methodologies and influence the future of neuromorphic computing. Working closely with design architects and circuit experts, you will define test strategies, implement fault coverage solutions, and ensure robust operation across the product lifecycle. An openness to learning new technologies and methodologies, such as asynchronous design techniques and using agentic tools for development and debug is essential.

Requirements

Bachelors and 6+ years OR Masters and 4+ years of hands-on DFT experience from architecture to silicon bring-up.
6+ years of experience of architecting the entire DFT stack including scan insertion, compression and ATPG vector generation.
4+ years of direct ownership of IP and SoC-level scan constructs, e.g. boundary scan (JTAG), TAP, BIST/MBIST.
1 year of experience in debugging post-silicon and driving circuit changes for testability and reliability improvements.

Nice To Haves

Experience in custom ASICS or AI/ML accelerator design.
Experience in post-silicon bin split, die-level cherry picking (DLCP) and fault grading.
Strong System-Verilog/System-C/OOP background with pre-silicon verification experience.
Experience in test time reduction techniques on automatic test equipment (ATE).
Experience in asynchronous architectures and circuits.
1+ year of experience using AI tools for setting up tool flows, debugging and improving overall productivity.

Responsibilities

Architect a complete DFT solution at the SoC level, compiling the requirements of both synchronous and asynchronous designs.
Lead the flow-development for scan-insertion and compression at partition and SoC levels.
Build a scalable framework spanning EDA tools, RTL and emulation models to generate high-quality test vectors and validate them pre-silicon.
Collaborate with designers to drive DFT/DFD/DFM features to ensure manufacturing readiness to support HVM.
Lead silicon power-on, enabling tester content, debugging failures and maintaining any tools/flows that are developed.