Design Automation Engineer - Neuromorphic Computing

Intel Corporation•Austin, TX

1d•$122,440 - $232,190•Hybrid

About The Position

For nearly a decade, Intel's Neuromorphic Computing Lab has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach. Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators. If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads.

Requirements

Bachelors and 4+ years OR Masters and 2+ years of experience in developing and deploying production quality tools, flows and methods for silicon design.
4+ years of experience in developing and maintaining the entire ASIC tool suite. E.g. synthesis, place and route, ATPG, FEV, RV, STA, LVS/DRC.
4+ years of experience with scripting languages such as Perl, TCL, Python, etc.
2+ years of experience in delivering multiple silicon tape-outs.

Nice To Haves

Strong System-Verilog/System-C/Object Oriented Programming background.
Experience with large scale FPGA platforms like HAPS and/or emulation frameworks like ZeBu.
1+ year of experience using AI tools for setting up tool flows, debugging and improving overall productivity.

Responsibilities

Enhance and maintain Loihi's asynchronous EDA tool flow by implementing design automation algorithms, software tools, utilities, and regression tests.
Support RTL designers, verification engineers and physical design engineers by providing automated solutions to achieve product quality and target KPIs.
Enable early SW development by setting up a scalable framework mapping silicon designs in simulation and emulation.
Write custom scripts to manipulate synthesis and physical design tools for low power/high performance custom designs.