Principle Hardware Design Engineer - Systems Engineering

Marvell•Santa Clara, CA

13h•$150,680 - $225,700

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. As a Hardware Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering provides IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of the printed circuit board (PCB) engineering team designing boards for many different groups at Marvell. Marvell is designing more complex chips and boards than our competitors, for higher speeds than anyone else. We’re on the leading edge of this technology and you’ll love being a part of this. The Signal Integrity Engineering candidate within the Marlborough Design Center will have the opportunity to contribute to the design, implementation, and check out of critical SOC validation boards. This includes setting SI specifications, SI implementation guidelines for internal and external design teams, and simulation of the design to ensure high-quality results. Additional opportunities include collaboration with the package design and signal integrity teams to ensure package and board parameters are well understood. This role is for an individual contributor who will join a diverse hardware and software group that owns the development and execution of package and validation board design and implementation.

Requirements

High speed diff pair design
PCIE Gen4 or PCIE Gen5 (PAM-4 okay too)
Experience with reference board design for chip validation
Knowledge of PCB design issues associated with high speed diff pair
Power controller design – low voltage, high current, multi-phase SMPS
Experience with Power Integrity analysis
Knowledge of SI tools – Sigrity, SI Soft, HFSS
Component Selection
Schematic capture and PCB Layout tools (Prefer Cadence Concept)
Cloud compute systems
PCIe Protocols
Clock generation and distribution
Familiar with Mechanical design concepts
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
Experience as Lead Signal Integrity Engineer.
Strong understanding of EM fundamentals. Modeling and analysis of transmission lines, via structures, high-speed connectors, and complex BGA packages.
Proficiency in 2D/3D EM tools such as Sigrity Suite or Ansys EM as well as HSPICE.
Familiarity with Real-Time scope, VBA, TDR.
Experience with analysis of 25Gbps SERDES.
Experience establishing Signal Integrity parameters to guide board routing team.
Customer facing experience with strong verbal and written communication skills.

Nice To Haves

Working knowledge of ADS, QSI/QDC, or Hyperlynx is a plus.
Experience setting up, running, and summarizing Power Integrity simulations is a plus.
Experience interfacing with characterization team to ensure design calculations can be collaborated with implemented board and package results is a plus.

Responsibilities

Design Reference board for PCIe Gen5/6 chip.
Select and implement power scheme
Capture Schematic
Work with PCB Layout house
Create enterprise server reference systems, using PCIe Gen5 CEM sockets, and EDSFF.
Work with customers to assist with their designs, and/or implement their designs.
Work with RTL team to understand and implement various features and interfaces.
Provide for programming of various memories
Participate in bring and debug of chips.
Make decisions about reference designs, including connectors, cables.
Work with external vendors for problems, and completing their designs.
Work with SI engineers.
Work with chip package vendor for package design input