Principle Hardware Design Engineer - Systems Engineering

YK Solutions•Santa Clara, CA

13h•Onsite

About The Position

As a Hardware Design Principal Engineer with a leading Engineering/Architecture organization, you'll be a member of the Central Engineering business group. Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of the printed circuit board (PCB) engineering team designing boards for many different groups. Additionally, our client is designing more complex chips and boards than competitors, for higher speeds than anyone else. The Signal Integrity Engineering candidate will have the opportunity to contribute to design, implementation, and check out of critical SOC validation boards. This includes setting SI specifications, SI implementation guidelines for internal and external design teams, and simulation of the design to ensure high quality results. Additional opportunities include collaboration with the package design and signal integrity teams to ensure package and board parameters are well understood. This role is for an individual contributor who will join a diverse hardware and software group that owns development and execution of package and validation board design and implementation.

Requirements

High speed differential pair design
PCIe Gen4 or PCIe Gen5 (PAM-4 acceptable)
Experience with reference board design for chip validation
Knowledge of PCB design issues associated with high speed differential pairs
Power controller design – low voltage, high current, multi-phase SMPS
Experience with Power Integrity analysis
Knowledge of SI tools – Sigrity, SI Soft, HFSS
Component selection
Schematic capture and PCB layout tools (Cadence Concept preferred)
Cloud compute systems
PCIe protocols
Clock generation and distribution
Familiarity with mechanical design concepts
Bachelor's degree in Computer Science, Electrical Engineering, or related fields with 5-10 years of related professional experience, OR Master's degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 3-5 years of experience
Experience as Lead Signal Integrity Engineer
Strong understanding of EM fundamentals, including modeling and analysis of transmission lines, via structures, high-speed connectors, and complex BGA packages
Proficiency in 2D/3D EM tools such as Sigrity Suite or Ansys EM, as well as HSPICE
Familiarity with real-time scope, VBA, and TDR
Experience with analysis of 25Gbps SERDES
Experience establishing Signal Integrity parameters to guide board routing team
Customer facing experience with strong verbal and written communication skills

Nice To Haves

Working knowledge of ADS, QSI/QDC, or Hyperlynx
Experience setting up, running, and summarizing Power Integrity simulations
Experience interfacing with characterization team to ensure design calculations can be collaborated with implemented board and package results

Responsibilities

Design reference board for PCIe Gen5/6 chip
Select and implement power scheme
Capture schematic
Work with PCB layout house
Create enterprise server reference systems, using PCIe Gen5 CEM sockets and EDSFF
Work with customers to assist with their designs and/or implement their designs
Work with RTL team to understand and implement various features and interfaces
Provide for programming of various memories
Participate in bring-up and debug of chips
Make decisions about reference designs, including connectors and cables
Work with external vendors for problems and completing their designs
Work with SI engineers
Work with chip package vendor for package design input
Setting SI specifications
SI implementation guidelines for internal and external design teams
Simulation of the design to ensure high quality results
Collaboration with the package design and signal integrity teams to ensure package and board parameters are well understood