Principal Verification Engineer

SiFive•Austin, TX

About The Position

SiFive is creating RISC-V based CPU IPs faster and cheaper than ever before by combining the best practices of rapid, iterative software design with the proven fidelity of hardware engineering. The Verification architect will ensure the fidelity of new highly configurable cores and other related IPs, for clients taking on exciting new use cases—like autonomous driving, 5G networking, wearables, or IoT.

Requirements

+12 years experience in the related fields.
Bachelor's, or Master's in Computer Science, Electrical Engineering, or a similar discipline.
Thorough understanding of the high-level verification flow methodology (test plan creation, test generation, failure analysis, coverage analysis, and closure).
Proficient in troubleshooting and possessing strong analytical capabilities.
Good interpersonal skills to listen to diverse points of view and influence people from different disciplines.
BS/MS/Ph.D in EE, CE or CS
12+ years relevant experience with Core/CPU functional verification
8+ years direct experience on memory management verification
Deep understand of computer architecture
Seasoned developer using object oriented programing principles

Nice To Haves

CPU core experience is a significant plus for this position.
Direct experience with microarchitecture, instruction set design, or CPU pipeline optimization is preferred.
Functional programming experience is not required but helpful.

Responsibilities

Adopting state-of-the-art verification methodologies to in-house designs in order to ensure that everything on SiFive’s integrated circuits work as intended.
Understanding the component parts of the system, working with architect team from early feature development stage to provide verification feedback for architect-for-verification.
Creating verification strategies for given features/components.
Participating in microarchitecture design phase with the design team for design-for-verification.
Brainstorming corner case scenario with Design and DV team to improve verification quality.
Working with DV leads to ensure the test plan captures the architect and design intents.
Ensuring verification quality through coverage metrics and other means.
Working on solving verification challenges of memory management units that are being reused across several different generations of the Cores, as well as IO memory management unit. This includes hypervisor, virtualization, and guest virtualization.